+201404xx 3.5
+ - Fixed several performance issues. Transfer rates up to 2.5MB/s are now
+ possible.
+ - Implemented the READ BUFFER scsi command for performance testing purposes.
+
20140418 3.4
- Critical fix for writes when using non-standard block sizes.
- Fix to ensure SCSI phase bits are set atomically.
As currently implemented:
-Sequential read: 930kb/sec Sequential write: 900kb/sec
+Sequential read: 2.5MB/s Sequential write: 900kb/sec
Tested with a 16GB class 10 SD card, via the commands:
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_RX_DMA_COMPLETE.c
+* Version 1.70
+*
+* Description:
+* API for controlling the state of an interrupt.
+*
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SCSI_RX_DMA_COMPLETE.h>
+
+#if !defined(SCSI_RX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Place your includes, defines and code here
+********************************************************************************/
+/* `#START SCSI_RX_DMA_COMPLETE_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE 16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Start
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_Start(void)
+{
+ /* For all we know the interrupt is active. */
+ SCSI_RX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SCSI_RX_DMA_COMPLETE Interrupt. */
+ SCSI_RX_DMA_COMPLETE_SetVector(&SCSI_RX_DMA_COMPLETE_Interrupt);
+
+ /* Set the priority. */
+ SCSI_RX_DMA_COMPLETE_SetPriority((uint8)SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SCSI_RX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_StartEx
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address)
+{
+ /* For all we know the interrupt is active. */
+ SCSI_RX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SCSI_RX_DMA_COMPLETE Interrupt. */
+ SCSI_RX_DMA_COMPLETE_SetVector(address);
+
+ /* Set the priority. */
+ SCSI_RX_DMA_COMPLETE_SetPriority((uint8)SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SCSI_RX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Stop
+********************************************************************************
+*
+* Summary:
+* Disables and removes the interrupt.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_Stop(void)
+{
+ /* Disable this interrupt. */
+ SCSI_RX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the passive one. */
+ SCSI_RX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Interrupt
+********************************************************************************
+*
+* Summary:
+* The default Interrupt Service Routine for SCSI_RX_DMA_COMPLETE.
+*
+* Add custom code between the coments to keep the next version of this file
+* from over writting your code.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+CY_ISR(SCSI_RX_DMA_COMPLETE_Interrupt)
+{
+ /* Place your Interrupt code here. */
+ /* `#START SCSI_RX_DMA_COMPLETE_Interrupt` */
+
+ /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_SetVector
+********************************************************************************
+*
+* Summary:
+* Change the ISR vector for the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
+* will override any effect this method would have had. To set the vector
+* before the component has been started use SCSI_RX_DMA_COMPLETE_StartEx instead.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_SetVector(cyisraddress address)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RX_DMA_COMPLETE__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_GetVector
+********************************************************************************
+*
+* Summary:
+* Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RX_DMA_COMPLETE__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_SetPriority
+********************************************************************************
+*
+* Summary:
+* Sets the Priority of the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start
+* or SCSI_RX_DMA_COMPLETE_StartEx will override any effect this method
+* would have had. This method should only be called after
+* SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called. To set
+* the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority)
+{
+ *SCSI_RX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_GetPriority
+********************************************************************************
+*
+* Summary:
+* Gets the Priority of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void)
+{
+ uint8 priority;
+
+
+ priority = *SCSI_RX_DMA_COMPLETE_INTC_PRIOR >> 5;
+
+ return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Enable
+********************************************************************************
+*
+* Summary:
+* Enables the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_Enable(void)
+{
+ /* Enable the general interrupt. */
+ *SCSI_RX_DMA_COMPLETE_INTC_SET_EN = SCSI_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_GetState
+********************************************************************************
+*
+* Summary:
+* Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* 1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SCSI_RX_DMA_COMPLETE_GetState(void)
+{
+ /* Get the state of the general interrupt. */
+ return ((*SCSI_RX_DMA_COMPLETE_INTC_SET_EN & (uint32)SCSI_RX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_Disable
+********************************************************************************
+*
+* Summary:
+* Disables the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_Disable(void)
+{
+ /* Disable the general interrupt. */
+ *SCSI_RX_DMA_COMPLETE_INTC_CLR_EN = SCSI_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_SetPending
+********************************************************************************
+*
+* Summary:
+* Causes the Interrupt to enter the pending state, a software method of
+* generating the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_SetPending(void)
+{
+ *SCSI_RX_DMA_COMPLETE_INTC_SET_PD = SCSI_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_RX_DMA_COMPLETE_ClearPending
+********************************************************************************
+*
+* Summary:
+* Clears a pending interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_RX_DMA_COMPLETE_ClearPending(void)
+{
+ *SCSI_RX_DMA_COMPLETE_INTC_CLR_PD = SCSI_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_RX_DMA_COMPLETE.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SCSI_RX_DMA_COMPLETE_H)
+#define CY_ISR_SCSI_RX_DMA_COMPLETE_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SCSI_RX_DMA_COMPLETE_Start(void);
+void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address);
+void SCSI_RX_DMA_COMPLETE_Stop(void);
+
+CY_ISR_PROTO(SCSI_RX_DMA_COMPLETE_Interrupt);
+
+void SCSI_RX_DMA_COMPLETE_SetVector(cyisraddress address);
+cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void);
+
+void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority);
+uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void);
+
+void SCSI_RX_DMA_COMPLETE_Enable(void);
+uint8 SCSI_RX_DMA_COMPLETE_GetState(void);
+void SCSI_RX_DMA_COMPLETE_Disable(void);
+
+void SCSI_RX_DMA_COMPLETE_SetPending(void);
+void SCSI_RX_DMA_COMPLETE_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_RX_DMA_COMPLETE ISR. */
+#define SCSI_RX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_VECT)
+
+/* Address of the SCSI_RX_DMA_COMPLETE ISR priority. */
+#define SCSI_RX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG)
+
+/* Priority of the SCSI_RX_DMA_COMPLETE interrupt. */
+#define SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_RX_DMA_COMPLETE interrupt. */
+#define SCSI_RX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_RX_DMA_COMPLETE interrupt. */
+#define SCSI_RX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SCSI_RX_DMA_COMPLETE interrupt state to pending. */
+#define SCSI_RX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_RX_DMA_COMPLETE interrupt. */
+#define SCSI_RX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SCSI_RX_DMA_COMPLETE_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/***************************************************************************
+* File Name: SCSI_RX_DMA_dma.c
+* Version 1.70
+*
+* Description:
+* Provides an API for the DMAC component. The API includes functions
+* for the DMA controller, DMA channels and Transfer Descriptors.
+*
+*
+* Note:
+* This module requires the developer to finish or fill in the auto
+* generated funcions and setup the dma channel and TD's.
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#include <CYLIB.H>
+#include <CYDMAC.H>
+#include <SCSI_RX_DMA_dma.H>
+
+
+
+/****************************************************************************
+*
+* The following defines are available in Cyfitter.h
+*
+*
+*
+* SCSI_RX_DMA__DRQ_CTL_REG
+*
+*
+* SCSI_RX_DMA__DRQ_NUMBER
+*
+* Number of TD's used by this channel.
+* SCSI_RX_DMA__NUMBEROF_TDS
+*
+* Priority of this channel.
+* SCSI_RX_DMA__PRIORITY
+*
+* True if SCSI_RX_DMA_TERMIN_SEL is used.
+* SCSI_RX_DMA__TERMIN_EN
+*
+* TERMIN interrupt line to signal terminate.
+* SCSI_RX_DMA__TERMIN_SEL
+*
+*
+* True if SCSI_RX_DMA_TERMOUT0_SEL is used.
+* SCSI_RX_DMA__TERMOUT0_EN
+*
+*
+* TERMOUT0 interrupt line to signal completion.
+* SCSI_RX_DMA__TERMOUT0_SEL
+*
+*
+* True if SCSI_RX_DMA_TERMOUT1_SEL is used.
+* SCSI_RX_DMA__TERMOUT1_EN
+*
+*
+* TERMOUT1 interrupt line to signal completion.
+* SCSI_RX_DMA__TERMOUT1_SEL
+*
+****************************************************************************/
+
+
+/* Zero based index of SCSI_RX_DMA dma channel */
+uint8 SCSI_RX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
+
+/*********************************************************************
+* Function Name: uint8 SCSI_RX_DMA_DmaInitalize
+**********************************************************************
+* Summary:
+* Allocates and initialises a channel of the DMAC to be used by the
+* caller.
+*
+* Parameters:
+* BurstCount.
+*
+*
+* ReqestPerBurst.
+*
+*
+* UpperSrcAddress.
+*
+*
+* UpperDestAddress.
+*
+*
+* Return:
+* The channel that can be used by the caller for DMA activity.
+* DMA_INVALID_CHANNEL (0xFF) if there are no channels left.
+*
+*
+*******************************************************************/
+uint8 SCSI_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress)
+{
+
+ /* Allocate a DMA channel. */
+ SCSI_RX_DMA_DmaHandle = (uint8)SCSI_RX_DMA__DRQ_NUMBER;
+
+ /* Configure the channel. */
+ (void)CyDmaChSetConfiguration(SCSI_RX_DMA_DmaHandle,
+ BurstCount,
+ ReqestPerBurst,
+ (uint8)SCSI_RX_DMA__TERMOUT0_SEL,
+ (uint8)SCSI_RX_DMA__TERMOUT1_SEL,
+ (uint8)SCSI_RX_DMA__TERMIN_SEL);
+
+ /* Set the extended address for the transfers */
+ (void)CyDmaChSetExtendedAddress(SCSI_RX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
+
+ /* Set the priority for this channel */
+ (void)CyDmaChPriority(SCSI_RX_DMA_DmaHandle, (uint8)SCSI_RX_DMA__PRIORITY);
+
+ return SCSI_RX_DMA_DmaHandle;
+}
+
+/*********************************************************************
+* Function Name: void SCSI_RX_DMA_DmaRelease
+**********************************************************************
+* Summary:
+* Frees the channel associated with SCSI_RX_DMA.
+*
+*
+* Parameters:
+* void.
+*
+*
+*
+* Return:
+* void.
+*
+*******************************************************************/
+void SCSI_RX_DMA_DmaRelease(void)
+{
+ /* Disable the channel */
+ (void)CyDmaChDisable(SCSI_RX_DMA_DmaHandle);
+}
+
--- /dev/null
+/******************************************************************************
+* File Name: SCSI_RX_DMA_dma.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the DMA Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#if !defined(CY_DMA_SCSI_RX_DMA_DMA_H__)
+#define CY_DMA_SCSI_RX_DMA_DMA_H__
+
+
+
+#include <CYDMAC.H>
+#include <CYFITTER.H>
+
+#define SCSI_RX_DMA__TD_TERMOUT_EN (((0 != SCSI_RX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
+ (SCSI_RX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
+
+/* Zero based index of SCSI_RX_DMA dma channel */
+extern uint8 SCSI_RX_DMA_DmaHandle;
+
+
+uint8 SCSI_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
+void SCSI_RX_DMA_DmaRelease(void) ;
+
+
+/* CY_DMA_SCSI_RX_DMA_DMA_H__ */
+#endif
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_TX_COMPLETE.c
+* Version 1.70
+*
+* Description:
+* API for controlling the state of an interrupt.
+*
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SCSI_TX_COMPLETE.h>
+
+#if !defined(SCSI_TX_COMPLETE__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Place your includes, defines and code here
+********************************************************************************/
+/* `#START SCSI_TX_COMPLETE_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE 16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_Start
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_Start(void)
+{
+ /* For all we know the interrupt is active. */
+ SCSI_TX_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SCSI_TX_COMPLETE Interrupt. */
+ SCSI_TX_COMPLETE_SetVector(&SCSI_TX_COMPLETE_Interrupt);
+
+ /* Set the priority. */
+ SCSI_TX_COMPLETE_SetPriority((uint8)SCSI_TX_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SCSI_TX_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_StartEx
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_StartEx(cyisraddress address)
+{
+ /* For all we know the interrupt is active. */
+ SCSI_TX_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SCSI_TX_COMPLETE Interrupt. */
+ SCSI_TX_COMPLETE_SetVector(address);
+
+ /* Set the priority. */
+ SCSI_TX_COMPLETE_SetPriority((uint8)SCSI_TX_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SCSI_TX_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_Stop
+********************************************************************************
+*
+* Summary:
+* Disables and removes the interrupt.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_Stop(void)
+{
+ /* Disable this interrupt. */
+ SCSI_TX_COMPLETE_Disable();
+
+ /* Set the ISR to point to the passive one. */
+ SCSI_TX_COMPLETE_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_Interrupt
+********************************************************************************
+*
+* Summary:
+* The default Interrupt Service Routine for SCSI_TX_COMPLETE.
+*
+* Add custom code between the coments to keep the next version of this file
+* from over writting your code.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+CY_ISR(SCSI_TX_COMPLETE_Interrupt)
+{
+ /* Place your Interrupt code here. */
+ /* `#START SCSI_TX_COMPLETE_Interrupt` */
+
+ /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_SetVector
+********************************************************************************
+*
+* Summary:
+* Change the ISR vector for the Interrupt. Note calling SCSI_TX_COMPLETE_Start
+* will override any effect this method would have had. To set the vector
+* before the component has been started use SCSI_TX_COMPLETE_StartEx instead.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_SetVector(cyisraddress address)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_COMPLETE__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_GetVector
+********************************************************************************
+*
+* Summary:
+* Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SCSI_TX_COMPLETE_GetVector(void)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_COMPLETE__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_SetPriority
+********************************************************************************
+*
+* Summary:
+* Sets the Priority of the Interrupt. Note calling SCSI_TX_COMPLETE_Start
+* or SCSI_TX_COMPLETE_StartEx will override any effect this method
+* would have had. This method should only be called after
+* SCSI_TX_COMPLETE_Start or SCSI_TX_COMPLETE_StartEx has been called. To set
+* the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_SetPriority(uint8 priority)
+{
+ *SCSI_TX_COMPLETE_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_GetPriority
+********************************************************************************
+*
+* Summary:
+* Gets the Priority of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 SCSI_TX_COMPLETE_GetPriority(void)
+{
+ uint8 priority;
+
+
+ priority = *SCSI_TX_COMPLETE_INTC_PRIOR >> 5;
+
+ return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_Enable
+********************************************************************************
+*
+* Summary:
+* Enables the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_Enable(void)
+{
+ /* Enable the general interrupt. */
+ *SCSI_TX_COMPLETE_INTC_SET_EN = SCSI_TX_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_GetState
+********************************************************************************
+*
+* Summary:
+* Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* 1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SCSI_TX_COMPLETE_GetState(void)
+{
+ /* Get the state of the general interrupt. */
+ return ((*SCSI_TX_COMPLETE_INTC_SET_EN & (uint32)SCSI_TX_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_Disable
+********************************************************************************
+*
+* Summary:
+* Disables the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_Disable(void)
+{
+ /* Disable the general interrupt. */
+ *SCSI_TX_COMPLETE_INTC_CLR_EN = SCSI_TX_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_SetPending
+********************************************************************************
+*
+* Summary:
+* Causes the Interrupt to enter the pending state, a software method of
+* generating the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_SetPending(void)
+{
+ *SCSI_TX_COMPLETE_INTC_SET_PD = SCSI_TX_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_COMPLETE_ClearPending
+********************************************************************************
+*
+* Summary:
+* Clears a pending interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_COMPLETE_ClearPending(void)
+{
+ *SCSI_TX_COMPLETE_INTC_CLR_PD = SCSI_TX_COMPLETE__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_TX_COMPLETE.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SCSI_TX_COMPLETE_H)
+#define CY_ISR_SCSI_TX_COMPLETE_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SCSI_TX_COMPLETE_Start(void);
+void SCSI_TX_COMPLETE_StartEx(cyisraddress address);
+void SCSI_TX_COMPLETE_Stop(void);
+
+CY_ISR_PROTO(SCSI_TX_COMPLETE_Interrupt);
+
+void SCSI_TX_COMPLETE_SetVector(cyisraddress address);
+cyisraddress SCSI_TX_COMPLETE_GetVector(void);
+
+void SCSI_TX_COMPLETE_SetPriority(uint8 priority);
+uint8 SCSI_TX_COMPLETE_GetPriority(void);
+
+void SCSI_TX_COMPLETE_Enable(void);
+uint8 SCSI_TX_COMPLETE_GetState(void);
+void SCSI_TX_COMPLETE_Disable(void);
+
+void SCSI_TX_COMPLETE_SetPending(void);
+void SCSI_TX_COMPLETE_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_TX_COMPLETE ISR. */
+#define SCSI_TX_COMPLETE_INTC_VECTOR ((reg32 *) SCSI_TX_COMPLETE__INTC_VECT)
+
+/* Address of the SCSI_TX_COMPLETE ISR priority. */
+#define SCSI_TX_COMPLETE_INTC_PRIOR ((reg8 *) SCSI_TX_COMPLETE__INTC_PRIOR_REG)
+
+/* Priority of the SCSI_TX_COMPLETE interrupt. */
+#define SCSI_TX_COMPLETE_INTC_PRIOR_NUMBER SCSI_TX_COMPLETE__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_TX_COMPLETE interrupt. */
+#define SCSI_TX_COMPLETE_INTC_SET_EN ((reg32 *) SCSI_TX_COMPLETE__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_TX_COMPLETE interrupt. */
+#define SCSI_TX_COMPLETE_INTC_CLR_EN ((reg32 *) SCSI_TX_COMPLETE__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SCSI_TX_COMPLETE interrupt state to pending. */
+#define SCSI_TX_COMPLETE_INTC_SET_PD ((reg32 *) SCSI_TX_COMPLETE__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_TX_COMPLETE interrupt. */
+#define SCSI_TX_COMPLETE_INTC_CLR_PD ((reg32 *) SCSI_TX_COMPLETE__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SCSI_TX_COMPLETE_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_TX_DMA_COMPLETE.c
+* Version 1.70
+*
+* Description:
+* API for controlling the state of an interrupt.
+*
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SCSI_TX_DMA_COMPLETE.h>
+
+#if !defined(SCSI_TX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Place your includes, defines and code here
+********************************************************************************/
+/* `#START SCSI_TX_DMA_COMPLETE_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE 16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Start
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_Start(void)
+{
+ /* For all we know the interrupt is active. */
+ SCSI_TX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SCSI_TX_DMA_COMPLETE Interrupt. */
+ SCSI_TX_DMA_COMPLETE_SetVector(&SCSI_TX_DMA_COMPLETE_Interrupt);
+
+ /* Set the priority. */
+ SCSI_TX_DMA_COMPLETE_SetPriority((uint8)SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SCSI_TX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_StartEx
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address)
+{
+ /* For all we know the interrupt is active. */
+ SCSI_TX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SCSI_TX_DMA_COMPLETE Interrupt. */
+ SCSI_TX_DMA_COMPLETE_SetVector(address);
+
+ /* Set the priority. */
+ SCSI_TX_DMA_COMPLETE_SetPriority((uint8)SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SCSI_TX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Stop
+********************************************************************************
+*
+* Summary:
+* Disables and removes the interrupt.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_Stop(void)
+{
+ /* Disable this interrupt. */
+ SCSI_TX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the passive one. */
+ SCSI_TX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Interrupt
+********************************************************************************
+*
+* Summary:
+* The default Interrupt Service Routine for SCSI_TX_DMA_COMPLETE.
+*
+* Add custom code between the coments to keep the next version of this file
+* from over writting your code.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+CY_ISR(SCSI_TX_DMA_COMPLETE_Interrupt)
+{
+ /* Place your Interrupt code here. */
+ /* `#START SCSI_TX_DMA_COMPLETE_Interrupt` */
+
+ /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_SetVector
+********************************************************************************
+*
+* Summary:
+* Change the ISR vector for the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
+* will override any effect this method would have had. To set the vector
+* before the component has been started use SCSI_TX_DMA_COMPLETE_StartEx instead.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_DMA_COMPLETE__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_GetVector
+********************************************************************************
+*
+* Summary:
+* Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_DMA_COMPLETE__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_SetPriority
+********************************************************************************
+*
+* Summary:
+* Sets the Priority of the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start
+* or SCSI_TX_DMA_COMPLETE_StartEx will override any effect this method
+* would have had. This method should only be called after
+* SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called. To set
+* the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority)
+{
+ *SCSI_TX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_GetPriority
+********************************************************************************
+*
+* Summary:
+* Gets the Priority of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void)
+{
+ uint8 priority;
+
+
+ priority = *SCSI_TX_DMA_COMPLETE_INTC_PRIOR >> 5;
+
+ return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Enable
+********************************************************************************
+*
+* Summary:
+* Enables the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_Enable(void)
+{
+ /* Enable the general interrupt. */
+ *SCSI_TX_DMA_COMPLETE_INTC_SET_EN = SCSI_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_GetState
+********************************************************************************
+*
+* Summary:
+* Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* 1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SCSI_TX_DMA_COMPLETE_GetState(void)
+{
+ /* Get the state of the general interrupt. */
+ return ((*SCSI_TX_DMA_COMPLETE_INTC_SET_EN & (uint32)SCSI_TX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_Disable
+********************************************************************************
+*
+* Summary:
+* Disables the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_Disable(void)
+{
+ /* Disable the general interrupt. */
+ *SCSI_TX_DMA_COMPLETE_INTC_CLR_EN = SCSI_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_SetPending
+********************************************************************************
+*
+* Summary:
+* Causes the Interrupt to enter the pending state, a software method of
+* generating the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_SetPending(void)
+{
+ *SCSI_TX_DMA_COMPLETE_INTC_SET_PD = SCSI_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_TX_DMA_COMPLETE_ClearPending
+********************************************************************************
+*
+* Summary:
+* Clears a pending interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_TX_DMA_COMPLETE_ClearPending(void)
+{
+ *SCSI_TX_DMA_COMPLETE_INTC_CLR_PD = SCSI_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_TX_DMA_COMPLETE.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SCSI_TX_DMA_COMPLETE_H)
+#define CY_ISR_SCSI_TX_DMA_COMPLETE_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SCSI_TX_DMA_COMPLETE_Start(void);
+void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address);
+void SCSI_TX_DMA_COMPLETE_Stop(void);
+
+CY_ISR_PROTO(SCSI_TX_DMA_COMPLETE_Interrupt);
+
+void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address);
+cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void);
+
+void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority);
+uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void);
+
+void SCSI_TX_DMA_COMPLETE_Enable(void);
+uint8 SCSI_TX_DMA_COMPLETE_GetState(void);
+void SCSI_TX_DMA_COMPLETE_Disable(void);
+
+void SCSI_TX_DMA_COMPLETE_SetPending(void);
+void SCSI_TX_DMA_COMPLETE_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_TX_DMA_COMPLETE ISR. */
+#define SCSI_TX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_VECT)
+
+/* Address of the SCSI_TX_DMA_COMPLETE ISR priority. */
+#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG)
+
+/* Priority of the SCSI_TX_DMA_COMPLETE interrupt. */
+#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_TX_DMA_COMPLETE interrupt. */
+#define SCSI_TX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_TX_DMA_COMPLETE interrupt. */
+#define SCSI_TX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SCSI_TX_DMA_COMPLETE interrupt state to pending. */
+#define SCSI_TX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_TX_DMA_COMPLETE interrupt. */
+#define SCSI_TX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SCSI_TX_DMA_COMPLETE_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/***************************************************************************
+* File Name: SCSI_TX_DMA_dma.c
+* Version 1.70
+*
+* Description:
+* Provides an API for the DMAC component. The API includes functions
+* for the DMA controller, DMA channels and Transfer Descriptors.
+*
+*
+* Note:
+* This module requires the developer to finish or fill in the auto
+* generated funcions and setup the dma channel and TD's.
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#include <CYLIB.H>
+#include <CYDMAC.H>
+#include <SCSI_TX_DMA_dma.H>
+
+
+
+/****************************************************************************
+*
+* The following defines are available in Cyfitter.h
+*
+*
+*
+* SCSI_TX_DMA__DRQ_CTL_REG
+*
+*
+* SCSI_TX_DMA__DRQ_NUMBER
+*
+* Number of TD's used by this channel.
+* SCSI_TX_DMA__NUMBEROF_TDS
+*
+* Priority of this channel.
+* SCSI_TX_DMA__PRIORITY
+*
+* True if SCSI_TX_DMA_TERMIN_SEL is used.
+* SCSI_TX_DMA__TERMIN_EN
+*
+* TERMIN interrupt line to signal terminate.
+* SCSI_TX_DMA__TERMIN_SEL
+*
+*
+* True if SCSI_TX_DMA_TERMOUT0_SEL is used.
+* SCSI_TX_DMA__TERMOUT0_EN
+*
+*
+* TERMOUT0 interrupt line to signal completion.
+* SCSI_TX_DMA__TERMOUT0_SEL
+*
+*
+* True if SCSI_TX_DMA_TERMOUT1_SEL is used.
+* SCSI_TX_DMA__TERMOUT1_EN
+*
+*
+* TERMOUT1 interrupt line to signal completion.
+* SCSI_TX_DMA__TERMOUT1_SEL
+*
+****************************************************************************/
+
+
+/* Zero based index of SCSI_TX_DMA dma channel */
+uint8 SCSI_TX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
+
+/*********************************************************************
+* Function Name: uint8 SCSI_TX_DMA_DmaInitalize
+**********************************************************************
+* Summary:
+* Allocates and initialises a channel of the DMAC to be used by the
+* caller.
+*
+* Parameters:
+* BurstCount.
+*
+*
+* ReqestPerBurst.
+*
+*
+* UpperSrcAddress.
+*
+*
+* UpperDestAddress.
+*
+*
+* Return:
+* The channel that can be used by the caller for DMA activity.
+* DMA_INVALID_CHANNEL (0xFF) if there are no channels left.
+*
+*
+*******************************************************************/
+uint8 SCSI_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress)
+{
+
+ /* Allocate a DMA channel. */
+ SCSI_TX_DMA_DmaHandle = (uint8)SCSI_TX_DMA__DRQ_NUMBER;
+
+ /* Configure the channel. */
+ (void)CyDmaChSetConfiguration(SCSI_TX_DMA_DmaHandle,
+ BurstCount,
+ ReqestPerBurst,
+ (uint8)SCSI_TX_DMA__TERMOUT0_SEL,
+ (uint8)SCSI_TX_DMA__TERMOUT1_SEL,
+ (uint8)SCSI_TX_DMA__TERMIN_SEL);
+
+ /* Set the extended address for the transfers */
+ (void)CyDmaChSetExtendedAddress(SCSI_TX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
+
+ /* Set the priority for this channel */
+ (void)CyDmaChPriority(SCSI_TX_DMA_DmaHandle, (uint8)SCSI_TX_DMA__PRIORITY);
+
+ return SCSI_TX_DMA_DmaHandle;
+}
+
+/*********************************************************************
+* Function Name: void SCSI_TX_DMA_DmaRelease
+**********************************************************************
+* Summary:
+* Frees the channel associated with SCSI_TX_DMA.
+*
+*
+* Parameters:
+* void.
+*
+*
+*
+* Return:
+* void.
+*
+*******************************************************************/
+void SCSI_TX_DMA_DmaRelease(void)
+{
+ /* Disable the channel */
+ (void)CyDmaChDisable(SCSI_TX_DMA_DmaHandle);
+}
+
--- /dev/null
+/******************************************************************************
+* File Name: SCSI_TX_DMA_dma.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the DMA Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#if !defined(CY_DMA_SCSI_TX_DMA_DMA_H__)
+#define CY_DMA_SCSI_TX_DMA_DMA_H__
+
+
+
+#include <CYDMAC.H>
+#include <CYFITTER.H>
+
+#define SCSI_TX_DMA__TD_TERMOUT_EN (((0 != SCSI_TX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
+ (SCSI_TX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
+
+/* Zero based index of SCSI_TX_DMA dma channel */
+extern uint8 SCSI_TX_DMA_DmaHandle;
+
+
+uint8 SCSI_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
+void SCSI_TX_DMA_DmaRelease(void) ;
+
+
+/* CY_DMA_SCSI_TX_DMA_DMA_H__ */
+#endif
\r
#define SDCard_INT_ON_SPI_DONE ((uint8) (0u << SDCard_STS_SPI_DONE_SHIFT))\r
#define SDCard_INT_ON_TX_EMPTY ((uint8) (0u << SDCard_STS_TX_FIFO_EMPTY_SHIFT))\r
-#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \\r
+#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (1u << \\r
SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))\r
#define SDCard_INT_ON_BYTE_COMP ((uint8) (0u << SDCard_STS_BYTE_COMPLETE_SHIFT))\r
#define SDCard_INT_ON_SPI_IDLE ((uint8) (0u << SDCard_STS_SPI_IDLE_SHIFT))\r
\r
#define SDCard_INT_ON_RX_FULL ((uint8) (0u << \\r
SDCard_STS_RX_FIFO_FULL_SHIFT))\r
-#define SDCard_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \\r
+#define SDCard_INT_ON_RX_NOT_EMPTY ((uint8) (1u << \\r
SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT))\r
#define SDCard_INT_ON_RX_OVER ((uint8) (0u << \\r
SDCard_STS_RX_FIFO_OVERRUN_SHIFT))\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD_Clk_Ctl.c \r
-* Version 1.70\r
-*\r
-* Description:\r
-* This file contains API to enable firmware control of a Control Register.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "SD_Clk_Ctl.h"\r
-\r
-#if !defined(SD_Clk_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Clk_Ctl_Write\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Write a byte to the Control Register.\r
-*\r
-* Parameters:\r
-* control: The value to be assigned to the Control Register.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-*******************************************************************************/\r
-void SD_Clk_Ctl_Write(uint8 control) \r
-{\r
- SD_Clk_Ctl_Control = control;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Clk_Ctl_Read\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Reads the current value assigned to the Control Register.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* Returns the current value in the Control Register.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_Clk_Ctl_Read(void) \r
-{\r
- return SD_Clk_Ctl_Control;\r
-}\r
-\r
-#endif /* End check for removal by optimization */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD_Clk_Ctl.h \r
-* Version 1.70\r
-*\r
-* Description:\r
-* This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_CONTROL_REG_SD_Clk_Ctl_H) /* CY_CONTROL_REG_SD_Clk_Ctl_H */\r
-#define CY_CONTROL_REG_SD_Clk_Ctl_H\r
-\r
-#include "cytypes.h"\r
-\r
-\r
-/***************************************\r
-* Function Prototypes \r
-***************************************/\r
-\r
-void SD_Clk_Ctl_Write(uint8 control) ;\r
-uint8 SD_Clk_Ctl_Read(void) ;\r
-\r
-\r
-/***************************************\r
-* Registers \r
-***************************************/\r
-\r
-/* Control Register */\r
-#define SD_Clk_Ctl_Control (* (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG )\r
-#define SD_Clk_Ctl_Control_PTR ( (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG )\r
-\r
-#endif /* End CY_CONTROL_REG_SD_Clk_Ctl_H */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD_Init_Clk.c\r
-* Version 2.10\r
-*\r
-* Description:\r
-* This file provides the source code to the API for the clock component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include <cydevice_trm.h>\r
-#include "SD_Init_Clk.h"\r
-\r
-/* Clock Distribution registers. */\r
-#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD)\r
-#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2)\r
-#define BCFG2_MASK (0x80u)\r
-#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK)\r
-#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK)\r
-\r
-#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP)\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_Start\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Starts the clock. Note that on startup, clocks may be already running if the\r
-* "Start on Reset" option is enabled in the DWR.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_Start(void) \r
-{\r
- /* Set the bit to enable the clock. */\r
- SD_Init_Clk_CLKEN |= SD_Init_Clk_CLKEN_MASK;\r
- SD_Init_Clk_CLKSTBY |= SD_Init_Clk_CLKSTBY_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_Stop\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Stops the clock and returns immediately. This API does not require the\r
-* source clock to be running but may return before the hardware is actually\r
-* disabled. If the settings of the clock are changed after calling this\r
-* function, the clock may glitch when it is started. To avoid the clock\r
-* glitch, use the StopBlock function.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_Stop(void) \r
-{\r
- /* Clear the bit to disable the clock. */\r
- SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK);\r
- SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK);\r
-}\r
-\r
-\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_StopBlock\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Stops the clock and waits for the hardware to actually be disabled before\r
-* returning. This ensures that the clock is never truncated (high part of the\r
-* cycle will terminate before the clock is disabled and the API returns).\r
-* Note that the source clock must be running or this API will never return as\r
-* a stopped clock cannot be disabled.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_StopBlock(void) \r
-{\r
- if ((SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK) != 0u)\r
- {\r
-#if HAS_CLKDIST_LD_DISABLE\r
- uint16 oldDivider;\r
-\r
- CLK_DIST_LD = 0u;\r
-\r
- /* Clear all the mask bits except ours. */\r
-#if defined(SD_Init_Clk__CFG3)\r
- CLK_DIST_AMASK = SD_Init_Clk_CLKEN_MASK;\r
- CLK_DIST_DMASK = 0x00u;\r
-#else\r
- CLK_DIST_DMASK = SD_Init_Clk_CLKEN_MASK;\r
- CLK_DIST_AMASK = 0x00u;\r
-#endif /* SD_Init_Clk__CFG3 */\r
-\r
- /* Clear mask of bus clock. */\r
- CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);\r
-\r
- oldDivider = CY_GET_REG16(SD_Init_Clk_DIV_PTR);\r
- CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);\r
- CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;\r
-\r
- /* Wait for clock to be disabled */\r
- while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
-\r
- /* Clear the bit to disable the clock. */\r
- SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK);\r
- SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK);\r
-\r
-#if HAS_CLKDIST_LD_DISABLE\r
- /* Clear the disable bit */\r
- CLK_DIST_LD = 0x00u;\r
- CY_SET_REG16(SD_Init_Clk_DIV_PTR, oldDivider);\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
- }\r
-}\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_StandbyPower\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Sets whether the clock is active in standby mode.\r
-*\r
-* Parameters:\r
-* state: 0 to disable clock during standby, nonzero to enable.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_StandbyPower(uint8 state) \r
-{\r
- if(state == 0u)\r
- {\r
- SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK);\r
- }\r
- else\r
- {\r
- SD_Init_Clk_CLKSTBY |= SD_Init_Clk_CLKSTBY_MASK;\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_SetDividerRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Modifies the clock divider and, thus, the frequency. When the clock divider\r
-* register is set to zero or changed from zero, the clock will be temporarily\r
-* disabled in order to change the SSS mode bit. If the clock is enabled when\r
-* SetDividerRegister is called, then the source clock must be running.\r
-*\r
-* Parameters:\r
-* clkDivider: Divider register value (0-65,535). This value is NOT the\r
-* divider; the clock hardware divides by clkDivider plus one. For example,\r
-* to divide the clock by 2, this parameter should be set to 1.\r
-* restart: If nonzero, restarts the clock divider: the current clock cycle\r
-* will be truncated and the new divide value will take effect immediately. If\r
-* zero, the new divide value will take effect at the end of the current clock\r
-* cycle.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart)\r
- \r
-{\r
- uint8 enabled;\r
-\r
- uint8 currSrc = SD_Init_Clk_GetSourceRegister();\r
- uint16 oldDivider = SD_Init_Clk_GetDividerRegister();\r
-\r
- if (clkDivider != oldDivider)\r
- {\r
- enabled = SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK;\r
-\r
- if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))\r
- {\r
- /* Moving to/from SSS requires correct ordering to prevent halting the clock */\r
- if (oldDivider == 0u)\r
- {\r
- /* Moving away from SSS, set the divider first so when SSS is cleared we */\r
- /* don't halt the clock. Using the shadow load isn't required as the */\r
- /* divider is ignored while SSS is set. */\r
- CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider);\r
- SD_Init_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS);\r
- }\r
- else\r
- {\r
- /* Moving to SSS, set SSS which then ignores the divider and we can set */\r
- /* it without bothering with the shadow load. */\r
- SD_Init_Clk_MOD_SRC |= CYCLK_SSS;\r
- CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider);\r
- }\r
- }\r
- else\r
- {\r
- \r
- if (enabled != 0u)\r
- {\r
- CLK_DIST_LD = 0x00u;\r
-\r
- /* Clear all the mask bits except ours. */\r
-#if defined(SD_Init_Clk__CFG3)\r
- CLK_DIST_AMASK = SD_Init_Clk_CLKEN_MASK;\r
- CLK_DIST_DMASK = 0x00u;\r
-#else\r
- CLK_DIST_DMASK = SD_Init_Clk_CLKEN_MASK;\r
- CLK_DIST_AMASK = 0x00u;\r
-#endif /* SD_Init_Clk__CFG3 */\r
- /* Clear mask of bus clock. */\r
- CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);\r
-\r
- /* If clock is currently enabled, disable it if async or going from N-to-1*/\r
- if (((SD_Init_Clk_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))\r
- {\r
-#if HAS_CLKDIST_LD_DISABLE\r
- CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);\r
- CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;\r
-\r
- /* Wait for clock to be disabled */\r
- while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
-\r
- SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK);\r
-\r
-#if HAS_CLKDIST_LD_DISABLE\r
- /* Clear the disable bit */\r
- CLK_DIST_LD = 0x00u;\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
- }\r
- }\r
-\r
- /* Load divide value. */\r
- if ((SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK) != 0u)\r
- {\r
- /* If the clock is still enabled, use the shadow registers */\r
- CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);\r
-\r
- CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));\r
- while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
- }\r
- else\r
- {\r
- /* If the clock is disabled, set the divider directly */\r
- CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider);\r
- SD_Init_Clk_CLKEN |= enabled;\r
- }\r
- }\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_GetDividerRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the clock divider register value.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* Divide value of the clock minus 1. For example, if the clock is set to\r
-* divide by 2, the return value will be 1.\r
-*\r
-*******************************************************************************/\r
-uint16 SD_Init_Clk_GetDividerRegister(void) \r
-{\r
- return CY_GET_REG16(SD_Init_Clk_DIV_PTR);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_SetModeRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Sets flags that control the operating mode of the clock. This function only\r
-* changes flags from 0 to 1; flags that are already 1 will remain unchanged.\r
-* To clear flags, use the ClearModeRegister function. The clock must be\r
-* disabled before changing the mode.\r
-*\r
-* Parameters:\r
-* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,\r
-* clkMode should be a set of the following optional bits or'ed together.\r
-* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will\r
-* occur when the divider count reaches half of the divide\r
-* value.\r
-* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock\r
-* is asserted for approximately half of its period. When\r
-* disabled, the output clock is asserted for one period of the\r
-* source clock.\r
-* - CYCLK_SYNC Enable output synchronization to master clock. This should\r
-* be enabled for all synchronous clocks.\r
-* See the Technical Reference Manual for details about setting the mode of\r
-* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_SetModeRegister(uint8 modeBitMask) \r
-{\r
- SD_Init_Clk_MOD_SRC |= modeBitMask & (uint8)SD_Init_Clk_MODE_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_ClearModeRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Clears flags that control the operating mode of the clock. This function\r
-* only changes flags from 1 to 0; flags that are already 0 will remain\r
-* unchanged. To set flags, use the SetModeRegister function. The clock must be\r
-* disabled before changing the mode.\r
-*\r
-* Parameters:\r
-* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,\r
-* clkMode should be a set of the following optional bits or'ed together.\r
-* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will\r
-* occur when the divider count reaches half of the divide\r
-* value.\r
-* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock\r
-* is asserted for approximately half of its period. When\r
-* disabled, the output clock is asserted for one period of the\r
-* source clock.\r
-* - CYCLK_SYNC Enable output synchronization to master clock. This should\r
-* be enabled for all synchronous clocks.\r
-* See the Technical Reference Manual for details about setting the mode of\r
-* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_ClearModeRegister(uint8 modeBitMask) \r
-{\r
- SD_Init_Clk_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_Init_Clk_MODE_MASK));\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_GetModeRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the clock mode register value.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* Bit mask representing the enabled mode bits. See the SetModeRegister and\r
-* ClearModeRegister descriptions for details about the mode bits.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_Init_Clk_GetModeRegister(void) \r
-{\r
- return SD_Init_Clk_MOD_SRC & (uint8)(SD_Init_Clk_MODE_MASK);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_SetSourceRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Sets the input source of the clock. The clock must be disabled before\r
-* changing the source. The old and new clock sources must be running.\r
-*\r
-* Parameters:\r
-* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the\r
-* following input sources:\r
-* - CYCLK_SRC_SEL_SYNC_DIG\r
-* - CYCLK_SRC_SEL_IMO\r
-* - CYCLK_SRC_SEL_XTALM\r
-* - CYCLK_SRC_SEL_ILO\r
-* - CYCLK_SRC_SEL_PLL\r
-* - CYCLK_SRC_SEL_XTALK\r
-* - CYCLK_SRC_SEL_DSI_G\r
-* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A\r
-* See the Technical Reference Manual for details on clock sources.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_SetSourceRegister(uint8 clkSource) \r
-{\r
- uint16 currDiv = SD_Init_Clk_GetDividerRegister();\r
- uint8 oldSrc = SD_Init_Clk_GetSourceRegister();\r
-\r
- if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && \r
- (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))\r
- {\r
- /* Switching to Master and divider is 1, set SSS, which will output master, */\r
- /* then set the source so we are consistent. */\r
- SD_Init_Clk_MOD_SRC |= CYCLK_SSS;\r
- SD_Init_Clk_MOD_SRC =\r
- (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource;\r
- }\r
- else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && \r
- (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))\r
- {\r
- /* Switching from Master to not and divider is 1, set source, so we don't */\r
- /* lock when we clear SSS. */\r
- SD_Init_Clk_MOD_SRC =\r
- (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource;\r
- SD_Init_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS);\r
- }\r
- else\r
- {\r
- SD_Init_Clk_MOD_SRC =\r
- (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource;\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_GetSourceRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the input source of the clock.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* The input source of the clock. See SetSourceRegister for details.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_Init_Clk_GetSourceRegister(void) \r
-{\r
- return SD_Init_Clk_MOD_SRC & SD_Init_Clk_SRC_SEL_MSK;\r
-}\r
-\r
-\r
-#if defined(SD_Init_Clk__CFG3)\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_SetPhaseRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Sets the phase delay of the analog clock. This function is only available\r
-* for analog clocks. The clock must be disabled before changing the phase\r
-* delay to avoid glitches.\r
-*\r
-* Parameters:\r
-* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.\r
-* clkPhase must be from 1 to 11 inclusive. Other values, including 0,\r
-* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 \r
-* produces a 10ns delay.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_Init_Clk_SetPhaseRegister(uint8 clkPhase) \r
-{\r
- SD_Init_Clk_PHASE = clkPhase & SD_Init_Clk_PHASE_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init_Clk_GetPhase\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the phase delay of the analog clock. This function is only available\r
-* for analog clocks.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* Phase of the analog clock. See SetPhaseRegister for details.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_Init_Clk_GetPhaseRegister(void) \r
-{\r
- return SD_Init_Clk_PHASE & SD_Init_Clk_PHASE_MASK;\r
-}\r
-\r
-#endif /* SD_Init_Clk__CFG3 */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD_Init_Clk.h\r
-* Version 2.10\r
-*\r
-* Description:\r
-* Provides the function and constant definitions for the clock component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_CLOCK_SD_Init_Clk_H)\r
-#define CY_CLOCK_SD_Init_Clk_H\r
-\r
-#include <cytypes.h>\r
-#include <cyfitter.h>\r
-\r
-\r
-/***************************************\r
-* Conditional Compilation Parameters\r
-***************************************/\r
-\r
-/* Check to see if required defines such as CY_PSOC5LP are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5LP)\r
- #error Component cy_clock_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5LP) */\r
-\r
-\r
-/***************************************\r
-* Function Prototypes\r
-***************************************/\r
-\r
-void SD_Init_Clk_Start(void) ;\r
-void SD_Init_Clk_Stop(void) ;\r
-\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
-void SD_Init_Clk_StopBlock(void) ;\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
-void SD_Init_Clk_StandbyPower(uint8 state) ;\r
-void SD_Init_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) \r
- ;\r
-uint16 SD_Init_Clk_GetDividerRegister(void) ;\r
-void SD_Init_Clk_SetModeRegister(uint8 modeBitMask) ;\r
-void SD_Init_Clk_ClearModeRegister(uint8 modeBitMask) ;\r
-uint8 SD_Init_Clk_GetModeRegister(void) ;\r
-void SD_Init_Clk_SetSourceRegister(uint8 clkSource) ;\r
-uint8 SD_Init_Clk_GetSourceRegister(void) ;\r
-#if defined(SD_Init_Clk__CFG3)\r
-void SD_Init_Clk_SetPhaseRegister(uint8 clkPhase) ;\r
-uint8 SD_Init_Clk_GetPhaseRegister(void) ;\r
-#endif /* defined(SD_Init_Clk__CFG3) */\r
-\r
-#define SD_Init_Clk_Enable() SD_Init_Clk_Start()\r
-#define SD_Init_Clk_Disable() SD_Init_Clk_Stop()\r
-#define SD_Init_Clk_SetDivider(clkDivider) SD_Init_Clk_SetDividerRegister(clkDivider, 1u)\r
-#define SD_Init_Clk_SetDividerValue(clkDivider) SD_Init_Clk_SetDividerRegister((clkDivider) - 1u, 1u)\r
-#define SD_Init_Clk_SetMode(clkMode) SD_Init_Clk_SetModeRegister(clkMode)\r
-#define SD_Init_Clk_SetSource(clkSource) SD_Init_Clk_SetSourceRegister(clkSource)\r
-#if defined(SD_Init_Clk__CFG3)\r
-#define SD_Init_Clk_SetPhase(clkPhase) SD_Init_Clk_SetPhaseRegister(clkPhase)\r
-#define SD_Init_Clk_SetPhaseValue(clkPhase) SD_Init_Clk_SetPhaseRegister((clkPhase) + 1u)\r
-#endif /* defined(SD_Init_Clk__CFG3) */\r
-\r
-\r
-/***************************************\r
-* Registers\r
-***************************************/\r
-\r
-/* Register to enable or disable the clock */\r
-#define SD_Init_Clk_CLKEN (* (reg8 *) SD_Init_Clk__PM_ACT_CFG)\r
-#define SD_Init_Clk_CLKEN_PTR ((reg8 *) SD_Init_Clk__PM_ACT_CFG)\r
-\r
-/* Register to enable or disable the clock */\r
-#define SD_Init_Clk_CLKSTBY (* (reg8 *) SD_Init_Clk__PM_STBY_CFG)\r
-#define SD_Init_Clk_CLKSTBY_PTR ((reg8 *) SD_Init_Clk__PM_STBY_CFG)\r
-\r
-/* Clock LSB divider configuration register. */\r
-#define SD_Init_Clk_DIV_LSB (* (reg8 *) SD_Init_Clk__CFG0)\r
-#define SD_Init_Clk_DIV_LSB_PTR ((reg8 *) SD_Init_Clk__CFG0)\r
-#define SD_Init_Clk_DIV_PTR ((reg16 *) SD_Init_Clk__CFG0)\r
-\r
-/* Clock MSB divider configuration register. */\r
-#define SD_Init_Clk_DIV_MSB (* (reg8 *) SD_Init_Clk__CFG1)\r
-#define SD_Init_Clk_DIV_MSB_PTR ((reg8 *) SD_Init_Clk__CFG1)\r
-\r
-/* Mode and source configuration register */\r
-#define SD_Init_Clk_MOD_SRC (* (reg8 *) SD_Init_Clk__CFG2)\r
-#define SD_Init_Clk_MOD_SRC_PTR ((reg8 *) SD_Init_Clk__CFG2)\r
-\r
-#if defined(SD_Init_Clk__CFG3)\r
-/* Analog clock phase configuration register */\r
-#define SD_Init_Clk_PHASE (* (reg8 *) SD_Init_Clk__CFG3)\r
-#define SD_Init_Clk_PHASE_PTR ((reg8 *) SD_Init_Clk__CFG3)\r
-#endif /* defined(SD_Init_Clk__CFG3) */\r
-\r
-\r
-/**************************************\r
-* Register Constants\r
-**************************************/\r
-\r
-/* Power manager register masks */\r
-#define SD_Init_Clk_CLKEN_MASK SD_Init_Clk__PM_ACT_MSK\r
-#define SD_Init_Clk_CLKSTBY_MASK SD_Init_Clk__PM_STBY_MSK\r
-\r
-/* CFG2 field masks */\r
-#define SD_Init_Clk_SRC_SEL_MSK SD_Init_Clk__CFG2_SRC_SEL_MASK\r
-#define SD_Init_Clk_MODE_MASK (~(SD_Init_Clk_SRC_SEL_MSK))\r
-\r
-#if defined(SD_Init_Clk__CFG3)\r
-/* CFG3 phase mask */\r
-#define SD_Init_Clk_PHASE_MASK SD_Init_Clk__CFG3_PHASE_DLY_MASK\r
-#endif /* defined(SD_Init_Clk__CFG3) */\r
-\r
-#endif /* CY_CLOCK_SD_Init_Clk_H */\r
-\r
-\r
-/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************
+* File Name: SD_RX_DMA_COMPLETE.c
+* Version 1.70
+*
+* Description:
+* API for controlling the state of an interrupt.
+*
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SD_RX_DMA_COMPLETE.h>
+
+#if !defined(SD_RX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Place your includes, defines and code here
+********************************************************************************/
+/* `#START SD_RX_DMA_COMPLETE_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE 16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Start
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_Start(void)
+{
+ /* For all we know the interrupt is active. */
+ SD_RX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SD_RX_DMA_COMPLETE Interrupt. */
+ SD_RX_DMA_COMPLETE_SetVector(&SD_RX_DMA_COMPLETE_Interrupt);
+
+ /* Set the priority. */
+ SD_RX_DMA_COMPLETE_SetPriority((uint8)SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SD_RX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_StartEx
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address)
+{
+ /* For all we know the interrupt is active. */
+ SD_RX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SD_RX_DMA_COMPLETE Interrupt. */
+ SD_RX_DMA_COMPLETE_SetVector(address);
+
+ /* Set the priority. */
+ SD_RX_DMA_COMPLETE_SetPriority((uint8)SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SD_RX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Stop
+********************************************************************************
+*
+* Summary:
+* Disables and removes the interrupt.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_Stop(void)
+{
+ /* Disable this interrupt. */
+ SD_RX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the passive one. */
+ SD_RX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Interrupt
+********************************************************************************
+*
+* Summary:
+* The default Interrupt Service Routine for SD_RX_DMA_COMPLETE.
+*
+* Add custom code between the coments to keep the next version of this file
+* from over writting your code.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+CY_ISR(SD_RX_DMA_COMPLETE_Interrupt)
+{
+ /* Place your Interrupt code here. */
+ /* `#START SD_RX_DMA_COMPLETE_Interrupt` */
+
+ /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_SetVector
+********************************************************************************
+*
+* Summary:
+* Change the ISR vector for the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
+* will override any effect this method would have had. To set the vector
+* before the component has been started use SD_RX_DMA_COMPLETE_StartEx instead.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_SetVector(cyisraddress address)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_RX_DMA_COMPLETE__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_GetVector
+********************************************************************************
+*
+* Summary:
+* Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SD_RX_DMA_COMPLETE_GetVector(void)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ return ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_RX_DMA_COMPLETE__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_SetPriority
+********************************************************************************
+*
+* Summary:
+* Sets the Priority of the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start
+* or SD_RX_DMA_COMPLETE_StartEx will override any effect this method
+* would have had. This method should only be called after
+* SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called. To set
+* the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority)
+{
+ *SD_RX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_GetPriority
+********************************************************************************
+*
+* Summary:
+* Gets the Priority of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 SD_RX_DMA_COMPLETE_GetPriority(void)
+{
+ uint8 priority;
+
+
+ priority = *SD_RX_DMA_COMPLETE_INTC_PRIOR >> 5;
+
+ return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Enable
+********************************************************************************
+*
+* Summary:
+* Enables the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_Enable(void)
+{
+ /* Enable the general interrupt. */
+ *SD_RX_DMA_COMPLETE_INTC_SET_EN = SD_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_GetState
+********************************************************************************
+*
+* Summary:
+* Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* 1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SD_RX_DMA_COMPLETE_GetState(void)
+{
+ /* Get the state of the general interrupt. */
+ return ((*SD_RX_DMA_COMPLETE_INTC_SET_EN & (uint32)SD_RX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_Disable
+********************************************************************************
+*
+* Summary:
+* Disables the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_Disable(void)
+{
+ /* Disable the general interrupt. */
+ *SD_RX_DMA_COMPLETE_INTC_CLR_EN = SD_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_SetPending
+********************************************************************************
+*
+* Summary:
+* Causes the Interrupt to enter the pending state, a software method of
+* generating the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_SetPending(void)
+{
+ *SD_RX_DMA_COMPLETE_INTC_SET_PD = SD_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_RX_DMA_COMPLETE_ClearPending
+********************************************************************************
+*
+* Summary:
+* Clears a pending interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_RX_DMA_COMPLETE_ClearPending(void)
+{
+ *SD_RX_DMA_COMPLETE_INTC_CLR_PD = SD_RX_DMA_COMPLETE__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SD_RX_DMA_COMPLETE.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SD_RX_DMA_COMPLETE_H)
+#define CY_ISR_SD_RX_DMA_COMPLETE_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SD_RX_DMA_COMPLETE_Start(void);
+void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address);
+void SD_RX_DMA_COMPLETE_Stop(void);
+
+CY_ISR_PROTO(SD_RX_DMA_COMPLETE_Interrupt);
+
+void SD_RX_DMA_COMPLETE_SetVector(cyisraddress address);
+cyisraddress SD_RX_DMA_COMPLETE_GetVector(void);
+
+void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority);
+uint8 SD_RX_DMA_COMPLETE_GetPriority(void);
+
+void SD_RX_DMA_COMPLETE_Enable(void);
+uint8 SD_RX_DMA_COMPLETE_GetState(void);
+void SD_RX_DMA_COMPLETE_Disable(void);
+
+void SD_RX_DMA_COMPLETE_SetPending(void);
+void SD_RX_DMA_COMPLETE_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SD_RX_DMA_COMPLETE ISR. */
+#define SD_RX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SD_RX_DMA_COMPLETE__INTC_VECT)
+
+/* Address of the SD_RX_DMA_COMPLETE ISR priority. */
+#define SD_RX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SD_RX_DMA_COMPLETE__INTC_PRIOR_REG)
+
+/* Priority of the SD_RX_DMA_COMPLETE interrupt. */
+#define SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SD_RX_DMA_COMPLETE interrupt. */
+#define SD_RX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SD_RX_DMA_COMPLETE__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SD_RX_DMA_COMPLETE interrupt. */
+#define SD_RX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SD_RX_DMA_COMPLETE interrupt state to pending. */
+#define SD_RX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SD_RX_DMA_COMPLETE__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SD_RX_DMA_COMPLETE interrupt. */
+#define SD_RX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SD_RX_DMA_COMPLETE_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/***************************************************************************
+* File Name: SD_RX_DMA_dma.c
+* Version 1.70
+*
+* Description:
+* Provides an API for the DMAC component. The API includes functions
+* for the DMA controller, DMA channels and Transfer Descriptors.
+*
+*
+* Note:
+* This module requires the developer to finish or fill in the auto
+* generated funcions and setup the dma channel and TD's.
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#include <CYLIB.H>
+#include <CYDMAC.H>
+#include <SD_RX_DMA_dma.H>
+
+
+
+/****************************************************************************
+*
+* The following defines are available in Cyfitter.h
+*
+*
+*
+* SD_RX_DMA__DRQ_CTL_REG
+*
+*
+* SD_RX_DMA__DRQ_NUMBER
+*
+* Number of TD's used by this channel.
+* SD_RX_DMA__NUMBEROF_TDS
+*
+* Priority of this channel.
+* SD_RX_DMA__PRIORITY
+*
+* True if SD_RX_DMA_TERMIN_SEL is used.
+* SD_RX_DMA__TERMIN_EN
+*
+* TERMIN interrupt line to signal terminate.
+* SD_RX_DMA__TERMIN_SEL
+*
+*
+* True if SD_RX_DMA_TERMOUT0_SEL is used.
+* SD_RX_DMA__TERMOUT0_EN
+*
+*
+* TERMOUT0 interrupt line to signal completion.
+* SD_RX_DMA__TERMOUT0_SEL
+*
+*
+* True if SD_RX_DMA_TERMOUT1_SEL is used.
+* SD_RX_DMA__TERMOUT1_EN
+*
+*
+* TERMOUT1 interrupt line to signal completion.
+* SD_RX_DMA__TERMOUT1_SEL
+*
+****************************************************************************/
+
+
+/* Zero based index of SD_RX_DMA dma channel */
+uint8 SD_RX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
+
+/*********************************************************************
+* Function Name: uint8 SD_RX_DMA_DmaInitalize
+**********************************************************************
+* Summary:
+* Allocates and initialises a channel of the DMAC to be used by the
+* caller.
+*
+* Parameters:
+* BurstCount.
+*
+*
+* ReqestPerBurst.
+*
+*
+* UpperSrcAddress.
+*
+*
+* UpperDestAddress.
+*
+*
+* Return:
+* The channel that can be used by the caller for DMA activity.
+* DMA_INVALID_CHANNEL (0xFF) if there are no channels left.
+*
+*
+*******************************************************************/
+uint8 SD_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress)
+{
+
+ /* Allocate a DMA channel. */
+ SD_RX_DMA_DmaHandle = (uint8)SD_RX_DMA__DRQ_NUMBER;
+
+ /* Configure the channel. */
+ (void)CyDmaChSetConfiguration(SD_RX_DMA_DmaHandle,
+ BurstCount,
+ ReqestPerBurst,
+ (uint8)SD_RX_DMA__TERMOUT0_SEL,
+ (uint8)SD_RX_DMA__TERMOUT1_SEL,
+ (uint8)SD_RX_DMA__TERMIN_SEL);
+
+ /* Set the extended address for the transfers */
+ (void)CyDmaChSetExtendedAddress(SD_RX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
+
+ /* Set the priority for this channel */
+ (void)CyDmaChPriority(SD_RX_DMA_DmaHandle, (uint8)SD_RX_DMA__PRIORITY);
+
+ return SD_RX_DMA_DmaHandle;
+}
+
+/*********************************************************************
+* Function Name: void SD_RX_DMA_DmaRelease
+**********************************************************************
+* Summary:
+* Frees the channel associated with SD_RX_DMA.
+*
+*
+* Parameters:
+* void.
+*
+*
+*
+* Return:
+* void.
+*
+*******************************************************************/
+void SD_RX_DMA_DmaRelease(void)
+{
+ /* Disable the channel */
+ (void)CyDmaChDisable(SD_RX_DMA_DmaHandle);
+}
+
--- /dev/null
+/******************************************************************************
+* File Name: SD_RX_DMA_dma.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the DMA Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#if !defined(CY_DMA_SD_RX_DMA_DMA_H__)
+#define CY_DMA_SD_RX_DMA_DMA_H__
+
+
+
+#include <CYDMAC.H>
+#include <CYFITTER.H>
+
+#define SD_RX_DMA__TD_TERMOUT_EN (((0 != SD_RX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
+ (SD_RX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
+
+/* Zero based index of SD_RX_DMA dma channel */
+extern uint8 SD_RX_DMA_DmaHandle;
+
+
+uint8 SD_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
+void SD_RX_DMA_DmaRelease(void) ;
+
+
+/* CY_DMA_SD_RX_DMA_DMA_H__ */
+#endif
--- /dev/null
+/*******************************************************************************
+* File Name: SD_TX_DMA_COMPLETE.c
+* Version 1.70
+*
+* Description:
+* API for controlling the state of an interrupt.
+*
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SD_TX_DMA_COMPLETE.h>
+
+#if !defined(SD_TX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Place your includes, defines and code here
+********************************************************************************/
+/* `#START SD_TX_DMA_COMPLETE_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE 16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Start
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_Start(void)
+{
+ /* For all we know the interrupt is active. */
+ SD_TX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SD_TX_DMA_COMPLETE Interrupt. */
+ SD_TX_DMA_COMPLETE_SetVector(&SD_TX_DMA_COMPLETE_Interrupt);
+
+ /* Set the priority. */
+ SD_TX_DMA_COMPLETE_SetPriority((uint8)SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SD_TX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_StartEx
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address)
+{
+ /* For all we know the interrupt is active. */
+ SD_TX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the SD_TX_DMA_COMPLETE Interrupt. */
+ SD_TX_DMA_COMPLETE_SetVector(address);
+
+ /* Set the priority. */
+ SD_TX_DMA_COMPLETE_SetPriority((uint8)SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SD_TX_DMA_COMPLETE_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Stop
+********************************************************************************
+*
+* Summary:
+* Disables and removes the interrupt.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_Stop(void)
+{
+ /* Disable this interrupt. */
+ SD_TX_DMA_COMPLETE_Disable();
+
+ /* Set the ISR to point to the passive one. */
+ SD_TX_DMA_COMPLETE_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Interrupt
+********************************************************************************
+*
+* Summary:
+* The default Interrupt Service Routine for SD_TX_DMA_COMPLETE.
+*
+* Add custom code between the coments to keep the next version of this file
+* from over writting your code.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+CY_ISR(SD_TX_DMA_COMPLETE_Interrupt)
+{
+ /* Place your Interrupt code here. */
+ /* `#START SD_TX_DMA_COMPLETE_Interrupt` */
+
+ /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_SetVector
+********************************************************************************
+*
+* Summary:
+* Change the ISR vector for the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
+* will override any effect this method would have had. To set the vector
+* before the component has been started use SD_TX_DMA_COMPLETE_StartEx instead.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_SetVector(cyisraddress address)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_TX_DMA_COMPLETE__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_GetVector
+********************************************************************************
+*
+* Summary:
+* Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SD_TX_DMA_COMPLETE_GetVector(void)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ return ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_TX_DMA_COMPLETE__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_SetPriority
+********************************************************************************
+*
+* Summary:
+* Sets the Priority of the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start
+* or SD_TX_DMA_COMPLETE_StartEx will override any effect this method
+* would have had. This method should only be called after
+* SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called. To set
+* the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority)
+{
+ *SD_TX_DMA_COMPLETE_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_GetPriority
+********************************************************************************
+*
+* Summary:
+* Gets the Priority of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 SD_TX_DMA_COMPLETE_GetPriority(void)
+{
+ uint8 priority;
+
+
+ priority = *SD_TX_DMA_COMPLETE_INTC_PRIOR >> 5;
+
+ return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Enable
+********************************************************************************
+*
+* Summary:
+* Enables the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_Enable(void)
+{
+ /* Enable the general interrupt. */
+ *SD_TX_DMA_COMPLETE_INTC_SET_EN = SD_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_GetState
+********************************************************************************
+*
+* Summary:
+* Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* 1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SD_TX_DMA_COMPLETE_GetState(void)
+{
+ /* Get the state of the general interrupt. */
+ return ((*SD_TX_DMA_COMPLETE_INTC_SET_EN & (uint32)SD_TX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_Disable
+********************************************************************************
+*
+* Summary:
+* Disables the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_Disable(void)
+{
+ /* Disable the general interrupt. */
+ *SD_TX_DMA_COMPLETE_INTC_CLR_EN = SD_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_SetPending
+********************************************************************************
+*
+* Summary:
+* Causes the Interrupt to enter the pending state, a software method of
+* generating the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_SetPending(void)
+{
+ *SD_TX_DMA_COMPLETE_INTC_SET_PD = SD_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SD_TX_DMA_COMPLETE_ClearPending
+********************************************************************************
+*
+* Summary:
+* Clears a pending interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SD_TX_DMA_COMPLETE_ClearPending(void)
+{
+ *SD_TX_DMA_COMPLETE_INTC_CLR_PD = SD_TX_DMA_COMPLETE__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SD_TX_DMA_COMPLETE.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SD_TX_DMA_COMPLETE_H)
+#define CY_ISR_SD_TX_DMA_COMPLETE_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SD_TX_DMA_COMPLETE_Start(void);
+void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address);
+void SD_TX_DMA_COMPLETE_Stop(void);
+
+CY_ISR_PROTO(SD_TX_DMA_COMPLETE_Interrupt);
+
+void SD_TX_DMA_COMPLETE_SetVector(cyisraddress address);
+cyisraddress SD_TX_DMA_COMPLETE_GetVector(void);
+
+void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority);
+uint8 SD_TX_DMA_COMPLETE_GetPriority(void);
+
+void SD_TX_DMA_COMPLETE_Enable(void);
+uint8 SD_TX_DMA_COMPLETE_GetState(void);
+void SD_TX_DMA_COMPLETE_Disable(void);
+
+void SD_TX_DMA_COMPLETE_SetPending(void);
+void SD_TX_DMA_COMPLETE_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SD_TX_DMA_COMPLETE ISR. */
+#define SD_TX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SD_TX_DMA_COMPLETE__INTC_VECT)
+
+/* Address of the SD_TX_DMA_COMPLETE ISR priority. */
+#define SD_TX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SD_TX_DMA_COMPLETE__INTC_PRIOR_REG)
+
+/* Priority of the SD_TX_DMA_COMPLETE interrupt. */
+#define SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SD_TX_DMA_COMPLETE interrupt. */
+#define SD_TX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SD_TX_DMA_COMPLETE__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SD_TX_DMA_COMPLETE interrupt. */
+#define SD_TX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SD_TX_DMA_COMPLETE interrupt state to pending. */
+#define SD_TX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SD_TX_DMA_COMPLETE__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SD_TX_DMA_COMPLETE interrupt. */
+#define SD_TX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SD_TX_DMA_COMPLETE_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/***************************************************************************
+* File Name: SD_TX_DMA_dma.c
+* Version 1.70
+*
+* Description:
+* Provides an API for the DMAC component. The API includes functions
+* for the DMA controller, DMA channels and Transfer Descriptors.
+*
+*
+* Note:
+* This module requires the developer to finish or fill in the auto
+* generated funcions and setup the dma channel and TD's.
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#include <CYLIB.H>
+#include <CYDMAC.H>
+#include <SD_TX_DMA_dma.H>
+
+
+
+/****************************************************************************
+*
+* The following defines are available in Cyfitter.h
+*
+*
+*
+* SD_TX_DMA__DRQ_CTL_REG
+*
+*
+* SD_TX_DMA__DRQ_NUMBER
+*
+* Number of TD's used by this channel.
+* SD_TX_DMA__NUMBEROF_TDS
+*
+* Priority of this channel.
+* SD_TX_DMA__PRIORITY
+*
+* True if SD_TX_DMA_TERMIN_SEL is used.
+* SD_TX_DMA__TERMIN_EN
+*
+* TERMIN interrupt line to signal terminate.
+* SD_TX_DMA__TERMIN_SEL
+*
+*
+* True if SD_TX_DMA_TERMOUT0_SEL is used.
+* SD_TX_DMA__TERMOUT0_EN
+*
+*
+* TERMOUT0 interrupt line to signal completion.
+* SD_TX_DMA__TERMOUT0_SEL
+*
+*
+* True if SD_TX_DMA_TERMOUT1_SEL is used.
+* SD_TX_DMA__TERMOUT1_EN
+*
+*
+* TERMOUT1 interrupt line to signal completion.
+* SD_TX_DMA__TERMOUT1_SEL
+*
+****************************************************************************/
+
+
+/* Zero based index of SD_TX_DMA dma channel */
+uint8 SD_TX_DMA_DmaHandle = DMA_INVALID_CHANNEL;
+
+/*********************************************************************
+* Function Name: uint8 SD_TX_DMA_DmaInitalize
+**********************************************************************
+* Summary:
+* Allocates and initialises a channel of the DMAC to be used by the
+* caller.
+*
+* Parameters:
+* BurstCount.
+*
+*
+* ReqestPerBurst.
+*
+*
+* UpperSrcAddress.
+*
+*
+* UpperDestAddress.
+*
+*
+* Return:
+* The channel that can be used by the caller for DMA activity.
+* DMA_INVALID_CHANNEL (0xFF) if there are no channels left.
+*
+*
+*******************************************************************/
+uint8 SD_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress)
+{
+
+ /* Allocate a DMA channel. */
+ SD_TX_DMA_DmaHandle = (uint8)SD_TX_DMA__DRQ_NUMBER;
+
+ /* Configure the channel. */
+ (void)CyDmaChSetConfiguration(SD_TX_DMA_DmaHandle,
+ BurstCount,
+ ReqestPerBurst,
+ (uint8)SD_TX_DMA__TERMOUT0_SEL,
+ (uint8)SD_TX_DMA__TERMOUT1_SEL,
+ (uint8)SD_TX_DMA__TERMIN_SEL);
+
+ /* Set the extended address for the transfers */
+ (void)CyDmaChSetExtendedAddress(SD_TX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress);
+
+ /* Set the priority for this channel */
+ (void)CyDmaChPriority(SD_TX_DMA_DmaHandle, (uint8)SD_TX_DMA__PRIORITY);
+
+ return SD_TX_DMA_DmaHandle;
+}
+
+/*********************************************************************
+* Function Name: void SD_TX_DMA_DmaRelease
+**********************************************************************
+* Summary:
+* Frees the channel associated with SD_TX_DMA.
+*
+*
+* Parameters:
+* void.
+*
+*
+*
+* Return:
+* void.
+*
+*******************************************************************/
+void SD_TX_DMA_DmaRelease(void)
+{
+ /* Disable the channel */
+ (void)CyDmaChDisable(SD_TX_DMA_DmaHandle);
+}
+
--- /dev/null
+/******************************************************************************
+* File Name: SD_TX_DMA_dma.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the DMA Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+#if !defined(CY_DMA_SD_TX_DMA_DMA_H__)
+#define CY_DMA_SD_TX_DMA_DMA_H__
+
+
+
+#include <CYDMAC.H>
+#include <CYFITTER.H>
+
+#define SD_TX_DMA__TD_TERMOUT_EN (((0 != SD_TX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \
+ (SD_TX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0))
+
+/* Zero based index of SD_TX_DMA dma channel */
+extern uint8 SD_TX_DMA_DmaHandle;
+
+
+uint8 SD_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ;
+void SD_TX_DMA_DmaRelease(void) ;
+
+
+/* CY_DMA_SD_TX_DMA_DMA_H__ */
+#endif
/* Debug_Timer_Interrupt */\r
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define Debug_Timer_Interrupt__INTC_MASK 0x01u\r
-#define Debug_Timer_Interrupt__INTC_NUMBER 0u\r
+#define Debug_Timer_Interrupt__INTC_MASK 0x02u\r
+#define Debug_Timer_Interrupt__INTC_NUMBER 1u\r
#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u\r
-#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_RX_DMA_COMPLETE */\r
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA_COMPLETE */\r
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x04u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 2u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
/* Debug_Timer_TimerHW */\r
#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0\r
#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1\r
#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1\r
#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0\r
\r
+/* SD_RX_DMA_COMPLETE */\r
+#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x08u\r
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 3u\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
+#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SD_TX_DMA_COMPLETE */\r
+#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x10u\r
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 4u\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
+#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
/* USBFS_bus_reset */\r
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
\r
/* SCSI_Out_Bits */\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
\r
/* USBFS_arb_int */\r
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB07_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB07_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB07_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB06_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB06_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB04_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB04_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB04_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB04_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB04_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB04_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1\r
\r
/* USBFS_dp_int */\r
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_In_DBx__DB7__SHIFT 1\r
#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW\r
\r
+/* SCSI_RX_DMA */\r
+#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SCSI_RX_DMA__DRQ_NUMBER 0u\r
+#define SCSI_RX_DMA__NUMBEROF_TDS 0u\r
+#define SCSI_RX_DMA__PRIORITY 2u\r
+#define SCSI_RX_DMA__TERMIN_EN 0u\r
+#define SCSI_RX_DMA__TERMIN_SEL 0u\r
+#define SCSI_RX_DMA__TERMOUT0_EN 1u\r
+#define SCSI_RX_DMA__TERMOUT0_SEL 0u\r
+#define SCSI_RX_DMA__TERMOUT1_EN 0u\r
+#define SCSI_RX_DMA__TERMOUT1_SEL 0u\r
+\r
+/* SCSI_TX_DMA */\r
+#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SCSI_TX_DMA__DRQ_NUMBER 1u\r
+#define SCSI_TX_DMA__NUMBEROF_TDS 0u\r
+#define SCSI_TX_DMA__PRIORITY 2u\r
+#define SCSI_TX_DMA__TERMIN_EN 0u\r
+#define SCSI_TX_DMA__TERMIN_SEL 0u\r
+#define SCSI_TX_DMA__TERMOUT0_EN 1u\r
+#define SCSI_TX_DMA__TERMOUT0_SEL 1u\r
+#define SCSI_TX_DMA__TERMOUT1_EN 0u\r
+#define SCSI_TX_DMA__TERMOUT1_SEL 0u\r
+\r
/* SD_Data_Clk */\r
#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0\r
#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1\r
/* scsiTarget */\r
#define scsiTarget_StatusReg__0__MASK 0x01u\r
#define scsiTarget_StatusReg__0__POS 0\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__2__POS 2\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__3__POS 3\r
-#define scsiTarget_StatusReg__MASK 0x0Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB13_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB13_ST\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB12_MSK\r
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB12_ST\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB12_CTL\r
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB12_CTL\r
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB12_MSK\r
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB12_13_A0\r
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB12_13_A1\r
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB12_13_D0\r
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB12_13_D1\r
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB12_13_F0\r
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB12_13_F1\r
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB12_A0_A1\r
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB12_A0\r
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB12_A1\r
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB12_D0_D1\r
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB12_D0\r
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB12_D1\r
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB12_F0_F1\r
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB12_F0\r
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB12_F1\r
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_StatusReg__4__MASK 0x10u\r
+#define scsiTarget_StatusReg__4__POS 4\r
+#define scsiTarget_StatusReg__MASK 0x1Fu\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__REMOVED 1u\r
\r
/* USBFS_ep_0 */\r
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
/* USBFS_ep_1 */\r
#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_1__INTC_MASK 0x02u\r
-#define USBFS_ep_1__INTC_NUMBER 1u\r
+#define USBFS_ep_1__INTC_MASK 0x20u\r
+#define USBFS_ep_1__INTC_NUMBER 5u\r
#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_2__INTC_MASK 0x04u\r
-#define USBFS_ep_2__INTC_NUMBER 2u\r
+#define USBFS_ep_2__INTC_MASK 0x40u\r
+#define USBFS_ep_2__INTC_NUMBER 6u\r
#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_3 */\r
#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_3__INTC_MASK 0x08u\r
-#define USBFS_ep_3__INTC_NUMBER 3u\r
+#define USBFS_ep_3__INTC_MASK 0x80u\r
+#define USBFS_ep_3__INTC_NUMBER 7u\r
#define USBFS_ep_3__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_4 */\r
#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_4__INTC_MASK 0x10u\r
-#define USBFS_ep_4__INTC_NUMBER 4u\r
+#define USBFS_ep_4__INTC_MASK 0x100u\r
+#define USBFS_ep_4__INTC_NUMBER 8u\r
#define USBFS_ep_4__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
+/* SD_RX_DMA */\r
+#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SD_RX_DMA__DRQ_NUMBER 2u\r
+#define SD_RX_DMA__NUMBEROF_TDS 0u\r
+#define SD_RX_DMA__PRIORITY 1u\r
+#define SD_RX_DMA__TERMIN_EN 0u\r
+#define SD_RX_DMA__TERMIN_SEL 0u\r
+#define SD_RX_DMA__TERMOUT0_EN 1u\r
+#define SD_RX_DMA__TERMOUT0_SEL 2u\r
+#define SD_RX_DMA__TERMOUT1_EN 0u\r
+#define SD_RX_DMA__TERMOUT1_SEL 0u\r
+\r
+/* SD_TX_DMA */\r
+#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SD_TX_DMA__DRQ_NUMBER 3u\r
+#define SD_TX_DMA__NUMBEROF_TDS 0u\r
+#define SD_TX_DMA__PRIORITY 2u\r
+#define SD_TX_DMA__TERMIN_EN 0u\r
+#define SD_TX_DMA__TERMIN_SEL 0u\r
+#define SD_TX_DMA__TERMOUT0_EN 1u\r
+#define SD_TX_DMA__TERMOUT0_SEL 3u\r
+#define SD_TX_DMA__TERMOUT1_EN 0u\r
+#define SD_TX_DMA__TERMOUT1_SEL 0u\r
+\r
/* USBFS_USB */\r
#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG\r
#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG\r
#define CYDEV_CHIP_FAMILY_PSOC5 3u\r
#define CYDEV_CHIP_DIE_PSOC5LP 4u\r
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP\r
-#define BCLK__BUS_CLK__HZ 60000000U\r
-#define BCLK__BUS_CLK__KHZ 60000U\r
-#define BCLK__BUS_CLK__MHZ 60U\r
+#define BCLK__BUS_CLK__HZ 50000000U\r
+#define BCLK__BUS_CLK__KHZ 50000U\r
+#define BCLK__BUS_CLK__MHZ 50U\r
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT\r
#define CYDEV_CHIP_DIE_LEOPARD 1u\r
#define CYDEV_CHIP_DIE_PANTHER 3u\r
#define CYDEV_ECC_ENABLE 0\r
#define CYDEV_HEAP_SIZE 0x0400\r
#define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
-#define CYDEV_INTR_RISING 0x00000001u\r
+#define CYDEV_INTR_RISING 0x0000001Eu\r
#define CYDEV_PROJ_TYPE 2\r
#define CYDEV_PROJ_TYPE_BOOTLOADER 1\r
#define CYDEV_PROJ_TYPE_LOADABLE 2\r
#define CYDEV_VIO2_MV 5000\r
#define CYDEV_VIO3 3.3\r
#define CYDEV_VIO3_MV 3300\r
-#define DMA_CHANNELS_USED__MASK0 0x00000000u\r
+#define DMA_CHANNELS_USED__MASK0 0x0000000Fu\r
#define CYDEV_BOOTLOADER_ENABLE 0\r
\r
#endif /* INCLUDED_CYFITTER_H */\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 35u\r
+#define CY_CFG_BASE_ADDR_COUNT 37u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
\r
\r
/* Configure Digital Clocks based on settings from Clock DWR */\r
- CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0001u);\r
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x10u);\r
- CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u);\r
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u);\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0000u);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u);\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0000u);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x58u);\r
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);\r
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0), 0x001Du);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB)));\r
\r
/* Configure PLL based on settings from Clock DWR */\r
- CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0919u);\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0B19u);\r
CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);\r
/* Wait up to 250us for the PLL to lock */\r
pllLock = 0u;\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);\r
\r
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x0Eu)));\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x0Fu)));\r
}\r
\r
\r
static const uint8 CYCODE BS_IOPINS0_6_VAL[] = {\r
0xF0u, 0x0Fu, 0x0Fu, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x01u};\r
\r
+ /* PHUB_CFGMEM1 Address: CYREG_PHUB_CFGMEM1_CFG0 Size (bytes): 4 */\r
+ static const uint8 CYCODE BS_PHUB_CFGMEM1_VAL[] = {\r
+ 0x00u, 0x01u, 0x00u, 0x00u};\r
+\r
+ /* PHUB_CFGMEM2 Address: CYREG_PHUB_CFGMEM2_CFG0 Size (bytes): 4 */\r
+ static const uint8 CYCODE BS_PHUB_CFGMEM2_VAL[] = {\r
+ 0x00u, 0x02u, 0x00u, 0x00u};\r
+\r
+ /* PHUB_CFGMEM3 Address: CYREG_PHUB_CFGMEM3_CFG0 Size (bytes): 4 */\r
+ static const uint8 CYCODE BS_PHUB_CFGMEM3_VAL[] = {\r
+ 0x00u, 0x03u, 0x00u, 0x00u};\r
+\r
#ifdef CYGlobalIntDisable\r
/* Disable interrupts by default. Let user enable if/when they want. */\r
CYGlobalIntDisable\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u));\r
/* Setup clocks based on selections from Clock DWR */\r
ClockSetup();\r
+ /* Set Flash Cycles based on newly configured 50.00MHz Bus Clock. */\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0xC1u : 0xC0u));\r
/* Enable/Disable Debug functionality based on settings from System DWR */\r
CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u));\r
\r
static const uint32 CYCODE cy_cfg_addr_table[] = {\r
0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
- 0x40005209u, /* Base address: 0x40005200 Count: 9 */\r
+ 0x4000520Au, /* Base address: 0x40005200 Count: 10 */\r
0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x4001004Au, /* Base address: 0x40010000 Count: 74 */\r
- 0x40010134u, /* Base address: 0x40010100 Count: 52 */\r
- 0x40010252u, /* Base address: 0x40010200 Count: 82 */\r
- 0x40010355u, /* Base address: 0x40010300 Count: 85 */\r
- 0x40010449u, /* Base address: 0x40010400 Count: 73 */\r
- 0x40010555u, /* Base address: 0x40010500 Count: 85 */\r
- 0x4001060Eu, /* Base address: 0x40010600 Count: 14 */\r
- 0x40010747u, /* Base address: 0x40010700 Count: 71 */\r
- 0x40010903u, /* Base address: 0x40010900 Count: 3 */\r
- 0x40010B0Cu, /* Base address: 0x40010B00 Count: 12 */\r
- 0x40010C45u, /* Base address: 0x40010C00 Count: 69 */\r
- 0x40010D4Du, /* Base address: 0x40010D00 Count: 77 */\r
- 0x40010F04u, /* Base address: 0x40010F00 Count: 4 */\r
- 0x40011501u, /* Base address: 0x40011500 Count: 1 */\r
- 0x40011657u, /* Base address: 0x40011600 Count: 87 */\r
- 0x40011753u, /* Base address: 0x40011700 Count: 83 */\r
- 0x40011903u, /* Base address: 0x40011900 Count: 3 */\r
- 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */\r
- 0x40014012u, /* Base address: 0x40014000 Count: 18 */\r
- 0x40014110u, /* Base address: 0x40014100 Count: 16 */\r
- 0x40014215u, /* Base address: 0x40014200 Count: 21 */\r
- 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */\r
- 0x40014410u, /* Base address: 0x40014400 Count: 16 */\r
- 0x40014517u, /* Base address: 0x40014500 Count: 23 */\r
- 0x40014607u, /* Base address: 0x40014600 Count: 7 */\r
- 0x4001470Au, /* Base address: 0x40014700 Count: 10 */\r
- 0x4001480Cu, /* Base address: 0x40014800 Count: 12 */\r
- 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
- 0x4001500Bu, /* Base address: 0x40015000 Count: 11 */\r
- 0x40015102u, /* Base address: 0x40015100 Count: 2 */\r
+ 0x40010052u, /* Base address: 0x40010000 Count: 82 */\r
+ 0x40010139u, /* Base address: 0x40010100 Count: 57 */\r
+ 0x40010241u, /* Base address: 0x40010200 Count: 65 */\r
+ 0x4001035Cu, /* Base address: 0x40010300 Count: 92 */\r
+ 0x40010417u, /* Base address: 0x40010400 Count: 23 */\r
+ 0x40010560u, /* Base address: 0x40010500 Count: 96 */\r
+ 0x4001065Du, /* Base address: 0x40010600 Count: 93 */\r
+ 0x40010754u, /* Base address: 0x40010700 Count: 84 */\r
+ 0x40010804u, /* Base address: 0x40010800 Count: 4 */\r
+ 0x4001090Eu, /* Base address: 0x40010900 Count: 14 */\r
+ 0x40010B12u, /* Base address: 0x40010B00 Count: 18 */\r
+ 0x40010C47u, /* Base address: 0x40010C00 Count: 71 */\r
+ 0x40010D45u, /* Base address: 0x40010D00 Count: 69 */\r
+ 0x40010F05u, /* Base address: 0x40010F00 Count: 5 */\r
+ 0x40011505u, /* Base address: 0x40011500 Count: 5 */\r
+ 0x4001164Cu, /* Base address: 0x40011600 Count: 76 */\r
+ 0x4001174Bu, /* Base address: 0x40011700 Count: 75 */\r
+ 0x4001190Au, /* Base address: 0x40011900 Count: 10 */\r
+ 0x40011B03u, /* Base address: 0x40011B00 Count: 3 */\r
+ 0x40014019u, /* Base address: 0x40014000 Count: 25 */\r
+ 0x40014117u, /* Base address: 0x40014100 Count: 23 */\r
+ 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */\r
+ 0x4001430Du, /* Base address: 0x40014300 Count: 13 */\r
+ 0x4001440Du, /* Base address: 0x40014400 Count: 13 */\r
+ 0x40014516u, /* Base address: 0x40014500 Count: 22 */\r
+ 0x40014608u, /* Base address: 0x40014600 Count: 8 */\r
+ 0x40014705u, /* Base address: 0x40014700 Count: 5 */\r
+ 0x40014807u, /* Base address: 0x40014800 Count: 7 */\r
+ 0x4001490Au, /* Base address: 0x40014900 Count: 10 */\r
+ 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
+ 0x40015005u, /* Base address: 0x40015000 Count: 5 */\r
+ 0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x36u, 0x02u},\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x36u},\r
- {0x00u, 0x13u},\r
- {0x01u, 0x05u},\r
- {0x19u, 0x04u},\r
+ {0x0Au, 0x1Bu},\r
+ {0x00u, 0x14u},\r
+ {0x01u, 0x01u},\r
+ {0x18u, 0x0Cu},\r
+ {0x19u, 0x08u},\r
{0x1Cu, 0x61u},\r
- {0x20u, 0xA8u},\r
- {0x21u, 0x60u},\r
- {0x30u, 0x09u},\r
- {0x31u, 0x0Au},\r
+ {0x20u, 0x60u},\r
+ {0x21u, 0xC0u},\r
+ {0x30u, 0x06u},\r
+ {0x31u, 0x0Cu},\r
{0x7Cu, 0x40u},\r
- {0x3Cu, 0x01u},\r
+ {0x23u, 0x02u},\r
{0x86u, 0x0Fu},\r
- {0x05u, 0x08u},\r
- {0x06u, 0x40u},\r
- {0x07u, 0x44u},\r
- {0x0Au, 0x10u},\r
- {0x0Cu, 0x55u},\r
- {0x0Du, 0x04u},\r
- {0x0Eu, 0xAAu},\r
- {0x0Fu, 0x09u},\r
- {0x11u, 0x4Du},\r
- {0x12u, 0x04u},\r
- {0x13u, 0xB2u},\r
- {0x16u, 0x20u},\r
- {0x1Au, 0x02u},\r
- {0x1Du, 0x20u},\r
- {0x1Fu, 0x90u},\r
- {0x22u, 0x01u},\r
- {0x2Au, 0x80u},\r
- {0x2Du, 0x10u},\r
- {0x2Eu, 0x08u},\r
- {0x2Fu, 0x22u},\r
- {0x30u, 0xC0u},\r
- {0x31u, 0xC0u},\r
- {0x32u, 0x0Cu},\r
- {0x33u, 0x03u},\r
- {0x34u, 0x30u},\r
- {0x35u, 0x3Cu},\r
- {0x36u, 0x03u},\r
- {0x3Eu, 0x55u},\r
- {0x3Fu, 0x15u},\r
+ {0x00u, 0x03u},\r
+ {0x01u, 0x09u},\r
+ {0x02u, 0x0Cu},\r
+ {0x03u, 0x24u},\r
+ {0x04u, 0x09u},\r
+ {0x06u, 0x06u},\r
+ {0x07u, 0x09u},\r
+ {0x08u, 0xFFu},\r
+ {0x09u, 0x40u},\r
+ {0x0Cu, 0x90u},\r
+ {0x0Eu, 0x60u},\r
+ {0x0Fu, 0x30u},\r
+ {0x10u, 0xFFu},\r
+ {0x11u, 0x09u},\r
+ {0x13u, 0x12u},\r
+ {0x14u, 0x05u},\r
+ {0x15u, 0x40u},\r
+ {0x16u, 0x0Au},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Cu, 0x0Fu},\r
+ {0x1Eu, 0xF0u},\r
+ {0x1Fu, 0x06u},\r
+ {0x20u, 0x50u},\r
+ {0x22u, 0xA0u},\r
+ {0x23u, 0x08u},\r
+ {0x25u, 0x80u},\r
+ {0x26u, 0xFFu},\r
+ {0x29u, 0x40u},\r
+ {0x2Cu, 0x30u},\r
+ {0x2Du, 0x40u},\r
+ {0x2Eu, 0xC0u},\r
+ {0x31u, 0x38u},\r
+ {0x32u, 0xFFu},\r
+ {0x33u, 0x40u},\r
+ {0x35u, 0x80u},\r
+ {0x37u, 0x07u},\r
+ {0x39u, 0x08u},\r
+ {0x3Eu, 0x04u},\r
+ {0x3Fu, 0x14u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x03u},\r
- {0x81u, 0x06u},\r
- {0x82u, 0x0Cu},\r
- {0x83u, 0x09u},\r
- {0x84u, 0x05u},\r
- {0x86u, 0x0Au},\r
- {0x87u, 0xFFu},\r
- {0x89u, 0x30u},\r
- {0x8Au, 0xFFu},\r
- {0x8Bu, 0xC0u},\r
- {0x8Cu, 0x0Fu},\r
- {0x8Du, 0x60u},\r
- {0x8Eu, 0xF0u},\r
- {0x8Fu, 0x90u},\r
- {0x90u, 0x90u},\r
- {0x91u, 0x0Fu},\r
- {0x92u, 0x60u},\r
- {0x93u, 0xF0u},\r
- {0x94u, 0xFFu},\r
- {0x95u, 0x50u},\r
- {0x97u, 0xA0u},\r
- {0x98u, 0xFFu},\r
- {0x99u, 0xFFu},\r
- {0xA1u, 0x03u},\r
- {0xA3u, 0x0Cu},\r
- {0xA4u, 0x50u},\r
- {0xA6u, 0xA0u},\r
- {0xA7u, 0xFFu},\r
- {0xA8u, 0x30u},\r
- {0xA9u, 0x05u},\r
- {0xAAu, 0xC0u},\r
- {0xABu, 0x0Au},\r
- {0xACu, 0x09u},\r
- {0xAEu, 0x06u},\r
- {0xB2u, 0xFFu},\r
- {0xB5u, 0xFFu},\r
- {0xBEu, 0x04u},\r
- {0xBFu, 0x10u},\r
+ {0x81u, 0x10u},\r
+ {0x83u, 0x20u},\r
+ {0x85u, 0x43u},\r
+ {0x86u, 0xC1u},\r
+ {0x87u, 0x04u},\r
+ {0x89u, 0x45u},\r
+ {0x8Au, 0x04u},\r
+ {0x8Bu, 0x02u},\r
+ {0x8Du, 0x08u},\r
+ {0x8Eu, 0x02u},\r
+ {0x90u, 0x24u},\r
+ {0x91u, 0x41u},\r
+ {0x92u, 0x90u},\r
+ {0x93u, 0x06u},\r
+ {0x95u, 0x04u},\r
+ {0x96u, 0x24u},\r
+ {0x97u, 0x03u},\r
+ {0x9Au, 0x18u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA0u, 0x01u},\r
+ {0xA2u, 0x02u},\r
+ {0xA6u, 0x20u},\r
+ {0xA8u, 0x24u},\r
+ {0xAAu, 0x48u},\r
+ {0xABu, 0x20u},\r
+ {0xB1u, 0x08u},\r
+ {0xB2u, 0xE0u},\r
+ {0xB3u, 0x07u},\r
+ {0xB4u, 0x1Cu},\r
+ {0xB5u, 0x30u},\r
+ {0xB6u, 0x03u},\r
+ {0xB7u, 0x40u},\r
+ {0xBBu, 0x08u},\r
+ {0xBEu, 0x40u},\r
+ {0xBFu, 0x51u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDCu, 0x01u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x08u},\r
- {0x01u, 0x10u},\r
- {0x03u, 0x01u},\r
- {0x05u, 0x02u},\r
- {0x06u, 0x28u},\r
- {0x07u, 0x03u},\r
- {0x08u, 0x01u},\r
- {0x0Au, 0x14u},\r
- {0x0Eu, 0x60u},\r
- {0x0Fu, 0x04u},\r
- {0x10u, 0x08u},\r
- {0x11u, 0x41u},\r
- {0x14u, 0x01u},\r
- {0x16u, 0x02u},\r
- {0x17u, 0x24u},\r
- {0x19u, 0x18u},\r
- {0x1Au, 0x80u},\r
- {0x1Bu, 0x80u},\r
- {0x1Du, 0x04u},\r
- {0x20u, 0x80u},\r
- {0x23u, 0x14u},\r
- {0x26u, 0x20u},\r
- {0x29u, 0x40u},\r
- {0x2Cu, 0x20u},\r
- {0x2Du, 0x13u},\r
- {0x2Eu, 0x20u},\r
- {0x33u, 0x41u},\r
- {0x34u, 0x10u},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x06u},\r
- {0x39u, 0x88u},\r
- {0x3Cu, 0x20u},\r
- {0x3Eu, 0x42u},\r
- {0x3Fu, 0x04u},\r
- {0x41u, 0xC0u},\r
- {0x68u, 0x10u},\r
- {0x69u, 0x40u},\r
- {0x6Au, 0x54u},\r
- {0x6Bu, 0x64u},\r
- {0x70u, 0x18u},\r
- {0x71u, 0x41u},\r
- {0x80u, 0x08u},\r
- {0x8Bu, 0x80u},\r
- {0x8Eu, 0x40u},\r
- {0xC0u, 0xF7u},\r
- {0xC2u, 0x7Eu},\r
- {0xC4u, 0xEBu},\r
- {0xCAu, 0xE8u},\r
- {0xCCu, 0xE9u},\r
- {0xCEu, 0xFAu},\r
- {0xE2u, 0x10u},\r
- {0xE6u, 0x05u},\r
- {0x01u, 0x03u},\r
- {0x03u, 0x0Cu},\r
- {0x04u, 0x30u},\r
- {0x06u, 0xC0u},\r
- {0x07u, 0xFFu},\r
- {0x0Au, 0xFFu},\r
- {0x0Bu, 0xFFu},\r
- {0x0Cu, 0x06u},\r
- {0x0Du, 0x90u},\r
- {0x0Eu, 0x09u},\r
- {0x0Fu, 0x60u},\r
- {0x10u, 0x60u},\r
- {0x11u, 0x0Fu},\r
- {0x12u, 0x90u},\r
- {0x13u, 0xF0u},\r
- {0x15u, 0x50u},\r
- {0x16u, 0xFFu},\r
- {0x17u, 0xA0u},\r
- {0x18u, 0xFFu},\r
- {0x19u, 0x30u},\r
- {0x1Bu, 0xC0u},\r
- {0x1Cu, 0x03u},\r
- {0x1Eu, 0x0Cu},\r
- {0x20u, 0x0Fu},\r
- {0x21u, 0x09u},\r
- {0x22u, 0xF0u},\r
- {0x23u, 0x06u},\r
- {0x24u, 0x50u},\r
- {0x26u, 0xA0u},\r
- {0x27u, 0xFFu},\r
- {0x28u, 0x05u},\r
- {0x29u, 0x05u},\r
- {0x2Au, 0x0Au},\r
- {0x2Bu, 0x0Au},\r
- {0x34u, 0xFFu},\r
- {0x35u, 0xFFu},\r
- {0x3Eu, 0x10u},\r
+ {0x00u, 0x80u},\r
+ {0x02u, 0xA0u},\r
+ {0x03u, 0x08u},\r
+ {0x05u, 0x14u},\r
+ {0x07u, 0x01u},\r
+ {0x08u, 0x40u},\r
+ {0x09u, 0x05u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Du, 0x25u},\r
+ {0x0Fu, 0x08u},\r
+ {0x11u, 0x84u},\r
+ {0x12u, 0x04u},\r
+ {0x13u, 0x22u},\r
+ {0x14u, 0x40u},\r
+ {0x15u, 0x20u},\r
+ {0x16u, 0x20u},\r
+ {0x18u, 0x10u},\r
+ {0x1Du, 0x24u},\r
+ {0x1Eu, 0x20u},\r
+ {0x1Fu, 0x80u},\r
+ {0x20u, 0x20u},\r
+ {0x22u, 0xD0u},\r
+ {0x23u, 0xC0u},\r
+ {0x24u, 0x40u},\r
+ {0x25u, 0x80u},\r
+ {0x26u, 0x04u},\r
+ {0x27u, 0x28u},\r
+ {0x28u, 0x08u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Bu, 0x22u},\r
+ {0x2Cu, 0x04u},\r
+ {0x31u, 0x01u},\r
+ {0x32u, 0x44u},\r
+ {0x33u, 0x10u},\r
+ {0x36u, 0x06u},\r
+ {0x37u, 0x80u},\r
+ {0x38u, 0x10u},\r
+ {0x39u, 0x0Au},\r
+ {0x3Bu, 0x40u},\r
+ {0x3Eu, 0x05u},\r
+ {0x3Fu, 0x90u},\r
+ {0x46u, 0x40u},\r
+ {0x47u, 0x01u},\r
+ {0x86u, 0x20u},\r
+ {0x87u, 0x02u},\r
+ {0x88u, 0x08u},\r
+ {0x8Cu, 0x40u},\r
+ {0x8Du, 0x01u},\r
+ {0x8Fu, 0x08u},\r
+ {0xC0u, 0xEFu},\r
+ {0xC2u, 0x7Du},\r
+ {0xC4u, 0x7Du},\r
+ {0xCAu, 0x2Fu},\r
+ {0xCCu, 0xDFu},\r
+ {0xCEu, 0xFFu},\r
+ {0xE2u, 0x08u},\r
+ {0xE6u, 0x72u},\r
+ {0x21u, 0x01u},\r
+ {0x35u, 0x01u},\r
{0x3Fu, 0x10u},\r
- {0x56u, 0x08u},\r
- {0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x0Du},\r
- {0x87u, 0x06u},\r
- {0x88u, 0x0Du},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0x0Du},\r
- {0x92u, 0x10u},\r
- {0x94u, 0x80u},\r
- {0x95u, 0x09u},\r
- {0x97u, 0x52u},\r
- {0x98u, 0x02u},\r
- {0x9Au, 0x54u},\r
- {0x9Cu, 0x02u},\r
- {0x9Eu, 0x0Du},\r
- {0x9Fu, 0x30u},\r
- {0xA0u, 0x0Du},\r
- {0xA1u, 0x09u},\r
- {0xA3u, 0x24u},\r
- {0xA4u, 0x01u},\r
- {0xA6u, 0x32u},\r
- {0xA7u, 0x01u},\r
- {0xA8u, 0x62u},\r
- {0xAAu, 0x08u},\r
- {0xABu, 0x49u},\r
- {0xACu, 0x0Du},\r
- {0xB0u, 0x70u},\r
- {0xB3u, 0x07u},\r
+ {0x80u, 0x80u},\r
+ {0x81u, 0x40u},\r
+ {0x84u, 0x02u},\r
+ {0x85u, 0x01u},\r
+ {0x8Au, 0x1Fu},\r
+ {0x8Bu, 0x20u},\r
+ {0x8Cu, 0x5Bu},\r
+ {0x8Du, 0x80u},\r
+ {0x8Eu, 0x24u},\r
+ {0x94u, 0x03u},\r
+ {0x95u, 0x08u},\r
+ {0x96u, 0x0Cu},\r
+ {0x97u, 0x12u},\r
+ {0x98u, 0x58u},\r
+ {0x99u, 0x0Bu},\r
+ {0x9Au, 0x24u},\r
+ {0x9Bu, 0x24u},\r
+ {0xA0u, 0x0Cu},\r
+ {0xA1u, 0x34u},\r
+ {0xA2u, 0x40u},\r
+ {0xA3u, 0x0Bu},\r
+ {0xA6u, 0x01u},\r
+ {0xA8u, 0x40u},\r
+ {0xAAu, 0x37u},\r
+ {0xABu, 0x3Fu},\r
+ {0xB0u, 0x1Fu},\r
+ {0xB1u, 0x80u},\r
+ {0xB2u, 0x20u},\r
+ {0xB3u, 0x38u},\r
{0xB4u, 0x80u},\r
- {0xB5u, 0x40u},\r
- {0xB6u, 0x0Fu},\r
- {0xB7u, 0x38u},\r
- {0xBAu, 0x80u},\r
- {0xBEu, 0x10u},\r
- {0xBFu, 0x10u},\r
- {0xD8u, 0x0Bu},\r
+ {0xB5u, 0x07u},\r
+ {0xB6u, 0x40u},\r
+ {0xB7u, 0x40u},\r
+ {0xBEu, 0x54u},\r
+ {0xBFu, 0x41u},\r
+ {0xC0u, 0x64u},\r
+ {0xC1u, 0x02u},\r
+ {0xC2u, 0x30u},\r
+ {0xC5u, 0xCDu},\r
+ {0xC6u, 0x2Eu},\r
+ {0xC7u, 0x0Fu},\r
+ {0xC8u, 0x1Fu},\r
+ {0xC9u, 0xFFu},\r
+ {0xCAu, 0xFFu},\r
+ {0xCBu, 0xFFu},\r
+ {0xCFu, 0x2Cu},\r
+ {0xD6u, 0x01u},\r
+ {0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDAu, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x19u},\r
+ {0xDCu, 0x11u},\r
+ {0xDDu, 0x01u},\r
{0xDFu, 0x01u},\r
- {0x03u, 0x19u},\r
- {0x06u, 0x0Au},\r
- {0x07u, 0x20u},\r
- {0x08u, 0x04u},\r
+ {0xE2u, 0xC0u},\r
+ {0xE6u, 0x80u},\r
+ {0xE8u, 0x40u},\r
+ {0xE9u, 0x40u},\r
+ {0xEEu, 0x08u},\r
+ {0x00u, 0x02u},\r
+ {0x01u, 0x08u},\r
+ {0x03u, 0x0Au},\r
{0x09u, 0x20u},\r
- {0x0Au, 0x81u},\r
- {0x0Eu, 0x50u},\r
- {0x0Fu, 0x05u},\r
+ {0x0Bu, 0x20u},\r
{0x10u, 0x80u},\r
- {0x11u, 0x40u},\r
- {0x13u, 0x18u},\r
- {0x14u, 0x40u},\r
- {0x15u, 0x10u},\r
- {0x17u, 0x06u},\r
- {0x19u, 0x20u},\r
- {0x1Au, 0x81u},\r
- {0x1Eu, 0x04u},\r
- {0x20u, 0x04u},\r
- {0x21u, 0x84u},\r
- {0x25u, 0x10u},\r
- {0x28u, 0x80u},\r
- {0x2Au, 0x10u},\r
- {0x2Bu, 0x10u},\r
- {0x2Cu, 0x20u},\r
- {0x2Du, 0x10u},\r
- {0x2Eu, 0x0Au},\r
- {0x31u, 0x80u},\r
- {0x32u, 0x04u},\r
- {0x37u, 0xE6u},\r
- {0x39u, 0x08u},\r
- {0x3Au, 0x20u},\r
- {0x3Du, 0x03u},\r
- {0x3Eu, 0x50u},\r
- {0x3Fu, 0x05u},\r
- {0x58u, 0x10u},\r
- {0x5Au, 0x10u},\r
- {0x5Fu, 0x80u},\r
- {0x61u, 0x01u},\r
- {0x62u, 0x02u},\r
- {0x64u, 0x02u},\r
- {0x6Bu, 0x02u},\r
- {0x6Cu, 0x02u},\r
- {0x78u, 0x02u},\r
- {0x82u, 0x02u},\r
- {0x83u, 0x10u},\r
- {0x84u, 0x80u},\r
- {0x86u, 0xA0u},\r
- {0x88u, 0x04u},\r
- {0x89u, 0x10u},\r
- {0x8Bu, 0x40u},\r
- {0x8Cu, 0x04u},\r
+ {0x11u, 0x04u},\r
+ {0x12u, 0x08u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x42u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Bu, 0x02u},\r
+ {0x21u, 0x34u},\r
+ {0x22u, 0x09u},\r
+ {0x23u, 0x05u},\r
+ {0x27u, 0x04u},\r
+ {0x29u, 0x02u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Du, 0x20u},\r
+ {0x2Fu, 0x80u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x08u},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x85u},\r
+ {0x41u, 0x11u},\r
+ {0x42u, 0x10u},\r
+ {0x43u, 0x02u},\r
+ {0x48u, 0x90u},\r
+ {0x49u, 0x08u},\r
+ {0x4Au, 0x08u},\r
+ {0x50u, 0x58u},\r
+ {0x5Au, 0xA2u},\r
+ {0x5Bu, 0x04u},\r
+ {0x60u, 0x44u},\r
+ {0x61u, 0x08u},\r
+ {0x63u, 0x01u},\r
+ {0x69u, 0x10u},\r
+ {0x6Au, 0x40u},\r
+ {0x6Bu, 0x50u},\r
+ {0x6Du, 0x64u},\r
+ {0x71u, 0x10u},\r
+ {0x72u, 0x22u},\r
+ {0x73u, 0x40u},\r
+ {0x81u, 0x40u},\r
+ {0x82u, 0x40u},\r
+ {0x87u, 0x80u},\r
+ {0x89u, 0x05u},\r
+ {0x8Au, 0x80u},\r
+ {0x8Bu, 0x80u},\r
+ {0x8Cu, 0x08u},\r
{0x8Du, 0x40u},\r
- {0x90u, 0x20u},\r
+ {0x8Fu, 0x08u},\r
+ {0x90u, 0x40u},\r
+ {0x92u, 0x20u},\r
+ {0x93u, 0x20u},\r
+ {0x94u, 0x80u},\r
+ {0x95u, 0x2Eu},\r
+ {0x96u, 0x0Du},\r
+ {0x97u, 0x10u},\r
+ {0x9Au, 0x44u},\r
+ {0x9Bu, 0x80u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Du, 0x11u},\r
+ {0x9Eu, 0x22u},\r
+ {0x9Fu, 0x12u},\r
+ {0xA1u, 0x80u},\r
+ {0xA2u, 0x90u},\r
+ {0xA3u, 0x04u},\r
+ {0xA4u, 0x48u},\r
+ {0xA5u, 0x44u},\r
+ {0xA6u, 0x02u},\r
+ {0xA7u, 0x20u},\r
+ {0xABu, 0x40u},\r
+ {0xACu, 0x10u},\r
+ {0xAFu, 0x91u},\r
+ {0xB0u, 0x04u},\r
+ {0xB7u, 0x08u},\r
+ {0xC0u, 0x0Fu},\r
+ {0xC2u, 0x06u},\r
+ {0xC4u, 0x0Eu},\r
+ {0xCAu, 0x85u},\r
+ {0xCCu, 0x06u},\r
+ {0xCEu, 0x0Fu},\r
+ {0xD0u, 0x07u},\r
+ {0xD2u, 0x04u},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x0Fu},\r
+ {0xE2u, 0x20u},\r
+ {0xE6u, 0x09u},\r
+ {0xEAu, 0x06u},\r
+ {0xEEu, 0x02u},\r
+ {0x85u, 0x02u},\r
+ {0x87u, 0x05u},\r
+ {0x8Fu, 0x02u},\r
+ {0x97u, 0x03u},\r
+ {0x9Au, 0x01u},\r
+ {0x9Fu, 0x0Cu},\r
+ {0xA1u, 0x02u},\r
+ {0xA2u, 0x04u},\r
+ {0xA3u, 0x08u},\r
+ {0xA4u, 0x05u},\r
+ {0xA6u, 0x0Au},\r
+ {0xAAu, 0x02u},\r
+ {0xAEu, 0x08u},\r
+ {0xB1u, 0x0Eu},\r
+ {0xB4u, 0x0Cu},\r
+ {0xB5u, 0x01u},\r
+ {0xB6u, 0x03u},\r
+ {0xBEu, 0x50u},\r
+ {0xBFu, 0x10u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDCu, 0x10u},\r
+ {0xDFu, 0x01u},\r
+ {0x01u, 0x41u},\r
+ {0x03u, 0x18u},\r
+ {0x04u, 0x80u},\r
+ {0x05u, 0x80u},\r
+ {0x08u, 0x48u},\r
+ {0x0Au, 0x86u},\r
+ {0x0Du, 0x80u},\r
+ {0x0Fu, 0x0Au},\r
+ {0x10u, 0x80u},\r
+ {0x12u, 0x02u},\r
+ {0x13u, 0x10u},\r
+ {0x14u, 0x01u},\r
+ {0x15u, 0x02u},\r
+ {0x17u, 0x28u},\r
+ {0x1Au, 0x82u},\r
+ {0x1Bu, 0x10u},\r
+ {0x1Fu, 0x90u},\r
+ {0x20u, 0x40u},\r
+ {0x22u, 0x10u},\r
+ {0x27u, 0x84u},\r
+ {0x29u, 0x02u},\r
+ {0x2Du, 0x02u},\r
+ {0x32u, 0x18u},\r
+ {0x33u, 0x40u},\r
+ {0x36u, 0x08u},\r
+ {0x37u, 0x80u},\r
+ {0x38u, 0x40u},\r
+ {0x39u, 0x10u},\r
+ {0x3Bu, 0x04u},\r
+ {0x3Fu, 0x44u},\r
+ {0x40u, 0x20u},\r
+ {0x42u, 0x04u},\r
+ {0x43u, 0x02u},\r
+ {0x49u, 0x04u},\r
+ {0x4Au, 0x02u},\r
+ {0x4Bu, 0x11u},\r
+ {0x50u, 0x08u},\r
+ {0x51u, 0x60u},\r
+ {0x53u, 0x01u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0xA0u},\r
+ {0x5Au, 0x01u},\r
+ {0x61u, 0x40u},\r
+ {0x64u, 0x02u},\r
+ {0x67u, 0x02u},\r
+ {0x79u, 0x02u},\r
+ {0x7Au, 0x80u},\r
+ {0x7Du, 0x08u},\r
+ {0x7Eu, 0x10u},\r
+ {0x80u, 0x08u},\r
+ {0x83u, 0x05u},\r
+ {0x85u, 0x40u},\r
+ {0x88u, 0x20u},\r
+ {0x8Bu, 0x10u},\r
+ {0x8Fu, 0x80u},\r
+ {0x90u, 0x80u},\r
+ {0x91u, 0x14u},\r
{0x92u, 0x40u},\r
- {0x93u, 0x04u},\r
- {0x95u, 0x19u},\r
- {0x98u, 0x08u},\r
- {0x99u, 0x05u},\r
- {0x9Bu, 0x24u},\r
- {0x9Cu, 0x10u},\r
- {0x9Eu, 0x0Au},\r
- {0x9Fu, 0x02u},\r
- {0xA0u, 0x08u},\r
- {0xA2u, 0x20u},\r
- {0xA4u, 0x24u},\r
- {0xA5u, 0x80u},\r
- {0xACu, 0x40u},\r
- {0xADu, 0x08u},\r
- {0xB3u, 0x10u},\r
+ {0x93u, 0x44u},\r
+ {0x96u, 0x0Cu},\r
+ {0x97u, 0x10u},\r
+ {0x98u, 0x04u},\r
+ {0x99u, 0x62u},\r
+ {0x9Au, 0x44u},\r
+ {0x9Bu, 0x68u},\r
+ {0xA0u, 0x10u},\r
+ {0xA1u, 0x80u},\r
+ {0xA2u, 0x98u},\r
+ {0xA3u, 0x04u},\r
+ {0xA4u, 0x40u},\r
+ {0xA5u, 0x04u},\r
+ {0xA6u, 0x02u},\r
+ {0xA7u, 0x40u},\r
+ {0xA9u, 0x29u},\r
+ {0xABu, 0x20u},\r
+ {0xACu, 0x84u},\r
+ {0xADu, 0x40u},\r
+ {0xB0u, 0x01u},\r
+ {0xB2u, 0x01u},\r
+ {0xB3u, 0x28u},\r
{0xB5u, 0x10u},\r
- {0xC0u, 0xE7u},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0x7Fu},\r
- {0xCAu, 0xE7u},\r
- {0xCCu, 0xEAu},\r
- {0xCEu, 0xF6u},\r
- {0xD6u, 0x10u},\r
- {0xD8u, 0x10u},\r
- {0xDEu, 0x01u},\r
- {0xE2u, 0x0Au},\r
- {0xE6u, 0x47u},\r
- {0xE8u, 0x02u},\r
- {0xEAu, 0x08u},\r
- {0xECu, 0x08u},\r
- {0xEEu, 0x80u},\r
- {0x01u, 0x44u},\r
- {0x05u, 0xE1u},\r
- {0x06u, 0x46u},\r
- {0x07u, 0x12u},\r
- {0x08u, 0x09u},\r
- {0x09u, 0x80u},\r
- {0x0Au, 0x12u},\r
- {0x0Bu, 0x5Fu},\r
- {0x0Du, 0x4Cu},\r
- {0x0Eu, 0x80u},\r
- {0x11u, 0x4Cu},\r
- {0x12u, 0x30u},\r
+ {0xB7u, 0x42u},\r
+ {0xC0u, 0x0Fu},\r
+ {0xC2u, 0x4Fu},\r
+ {0xC4u, 0xFBu},\r
+ {0xCAu, 0x81u},\r
+ {0xCCu, 0x5Eu},\r
+ {0xCEu, 0x5Eu},\r
+ {0xD0u, 0x07u},\r
+ {0xD2u, 0x0Cu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x08u},\r
+ {0xE0u, 0x80u},\r
+ {0xE2u, 0x40u},\r
+ {0xEAu, 0x03u},\r
+ {0xEEu, 0x54u},\r
+ {0x00u, 0x01u},\r
+ {0x03u, 0x9Fu},\r
+ {0x04u, 0x01u},\r
+ {0x07u, 0xFFu},\r
+ {0x08u, 0x04u},\r
+ {0x09u, 0x7Fu},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Cu, 0x01u},\r
+ {0x0Du, 0x90u},\r
+ {0x0Fu, 0x40u},\r
+ {0x11u, 0x1Fu},\r
+ {0x12u, 0x40u},\r
+ {0x13u, 0x20u},\r
+ {0x14u, 0xA2u},\r
+ {0x15u, 0x80u},\r
{0x16u, 0x08u},\r
- {0x17u, 0x4Cu},\r
- {0x19u, 0xB1u},\r
- {0x1Au, 0x09u},\r
- {0x1Bu, 0x0Eu},\r
- {0x1Cu, 0x09u},\r
- {0x1Du, 0x4Cu},\r
- {0x1Eu, 0x24u},\r
- {0x20u, 0x40u},\r
- {0x21u, 0x08u},\r
- {0x22u, 0x80u},\r
- {0x23u, 0x20u},\r
- {0x25u, 0x44u},\r
- {0x26u, 0x01u},\r
- {0x27u, 0x08u},\r
- {0x30u, 0x38u},\r
- {0x31u, 0x10u},\r
- {0x33u, 0x61u},\r
- {0x34u, 0x07u},\r
- {0x35u, 0x0Fu},\r
- {0x36u, 0xC0u},\r
- {0x37u, 0x80u},\r
- {0x3Bu, 0x0Cu},\r
+ {0x18u, 0x08u},\r
+ {0x1Au, 0x61u},\r
+ {0x1Bu, 0x60u},\r
+ {0x1Cu, 0x01u},\r
+ {0x1Du, 0xC0u},\r
+ {0x1Fu, 0x02u},\r
+ {0x20u, 0x07u},\r
+ {0x21u, 0xC0u},\r
+ {0x22u, 0xD8u},\r
+ {0x23u, 0x01u},\r
+ {0x25u, 0xC0u},\r
+ {0x27u, 0x04u},\r
+ {0x28u, 0x01u},\r
+ {0x29u, 0xC0u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Cu, 0x10u},\r
+ {0x30u, 0xE0u},\r
+ {0x36u, 0x3Fu},\r
+ {0x37u, 0xFFu},\r
+ {0x38u, 0x80u},\r
{0x3Eu, 0x40u},\r
- {0x3Fu, 0x41u},\r
- {0x54u, 0x09u},\r
+ {0x3Fu, 0x40u},\r
{0x58u, 0x04u},\r
- {0x59u, 0x0Bu},\r
- {0x5Bu, 0x0Bu},\r
- {0x5Cu, 0x91u},\r
- {0x5Du, 0x90u},\r
+ {0x59u, 0x04u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x38u},\r
- {0x85u, 0x04u},\r
- {0x88u, 0x01u},\r
- {0x89u, 0x04u},\r
- {0x8Au, 0x14u},\r
- {0x90u, 0x3Eu},\r
- {0x94u, 0x22u},\r
- {0x95u, 0x04u},\r
- {0x96u, 0x01u},\r
- {0x99u, 0x04u},\r
- {0x9Fu, 0x01u},\r
- {0xA4u, 0x09u},\r
- {0xA6u, 0x02u},\r
- {0xABu, 0x02u},\r
- {0xADu, 0x01u},\r
- {0xAFu, 0x02u},\r
- {0xB0u, 0x07u},\r
- {0xB1u, 0x03u},\r
- {0xB4u, 0x38u},\r
- {0xB7u, 0x04u},\r
- {0xB8u, 0x02u},\r
- {0xB9u, 0x80u},\r
- {0xBEu, 0x10u},\r
- {0xBFu, 0x41u},\r
- {0xD8u, 0x0Bu},\r
+ {0x80u, 0x56u},\r
+ {0x81u, 0x64u},\r
+ {0x84u, 0x52u},\r
+ {0x85u, 0x83u},\r
+ {0x86u, 0x04u},\r
+ {0x87u, 0x70u},\r
+ {0x88u, 0x50u},\r
+ {0x8Au, 0x06u},\r
+ {0x8Bu, 0xF5u},\r
+ {0x8Cu, 0x17u},\r
+ {0x8Du, 0x64u},\r
+ {0x8Eu, 0x28u},\r
+ {0x91u, 0x07u},\r
+ {0x93u, 0x90u},\r
+ {0x94u, 0x31u},\r
+ {0x95u, 0x40u},\r
+ {0x96u, 0x0Eu},\r
+ {0x97u, 0x02u},\r
+ {0x98u, 0x29u},\r
+ {0x99u, 0x24u},\r
+ {0x9Au, 0x16u},\r
+ {0x9Bu, 0x40u},\r
+ {0x9Du, 0x08u},\r
+ {0xA0u, 0x56u},\r
+ {0xA1u, 0x64u},\r
+ {0xA4u, 0x22u},\r
+ {0xA5u, 0x24u},\r
+ {0xA6u, 0x10u},\r
+ {0xA8u, 0x04u},\r
+ {0xABu, 0x64u},\r
+ {0xACu, 0x06u},\r
+ {0xADu, 0x08u},\r
+ {0xAEu, 0x50u},\r
+ {0xB0u, 0x40u},\r
+ {0xB1u, 0x71u},\r
+ {0xB2u, 0x30u},\r
+ {0xB3u, 0x07u},\r
+ {0xB4u, 0x0Fu},\r
+ {0xB5u, 0x08u},\r
+ {0xB7u, 0x80u},\r
+ {0xB8u, 0x20u},\r
+ {0xB9u, 0x20u},\r
+ {0xBAu, 0x08u},\r
+ {0xBBu, 0x0Cu},\r
+ {0xBEu, 0x01u},\r
+ {0xBFu, 0x40u},\r
+ {0xD4u, 0x40u},\r
+ {0xD6u, 0x04u},\r
+ {0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x09u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x20u},\r
+ {0x01u, 0x01u},\r
{0x02u, 0x02u},\r
- {0x03u, 0x20u},\r
- {0x04u, 0x02u},\r
- {0x05u, 0x10u},\r
- {0x08u, 0x80u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0xA0u},\r
- {0x0Bu, 0x04u},\r
- {0x0Eu, 0x80u},\r
+ {0x03u, 0x18u},\r
+ {0x05u, 0x08u},\r
+ {0x07u, 0x49u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Bu, 0x10u},\r
+ {0x0Cu, 0x80u},\r
+ {0x0Eu, 0x84u},\r
{0x0Fu, 0x10u},\r
- {0x10u, 0x40u},\r
- {0x11u, 0x08u},\r
- {0x17u, 0x08u},\r
- {0x19u, 0x20u},\r
- {0x1Au, 0x82u},\r
- {0x1Bu, 0x20u},\r
+ {0x10u, 0x98u},\r
+ {0x11u, 0x40u},\r
+ {0x15u, 0x82u},\r
+ {0x17u, 0x10u},\r
+ {0x18u, 0x08u},\r
+ {0x19u, 0x09u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Du, 0x40u},\r
{0x1Eu, 0x80u},\r
- {0x1Fu, 0x10u},\r
- {0x20u, 0x04u},\r
- {0x21u, 0x84u},\r
- {0x23u, 0x98u},\r
- {0x25u, 0x40u},\r
- {0x27u, 0x40u},\r
- {0x2Au, 0x0Bu},\r
- {0x2Cu, 0x02u},\r
- {0x2Fu, 0x04u},\r
- {0x30u, 0x80u},\r
- {0x31u, 0x10u},\r
- {0x33u, 0x09u},\r
- {0x35u, 0x04u},\r
- {0x36u, 0xA0u},\r
- {0x38u, 0x04u},\r
- {0x39u, 0x41u},\r
+ {0x21u, 0x01u},\r
+ {0x22u, 0x62u},\r
+ {0x23u, 0x18u},\r
+ {0x25u, 0x80u},\r
+ {0x28u, 0x10u},\r
+ {0x29u, 0x48u},\r
+ {0x2Bu, 0x88u},\r
+ {0x2Cu, 0xA0u},\r
+ {0x2Fu, 0x08u},\r
+ {0x30u, 0x28u},\r
+ {0x31u, 0x80u},\r
+ {0x32u, 0x02u},\r
+ {0x35u, 0x08u},\r
+ {0x36u, 0x22u},\r
+ {0x37u, 0x40u},\r
+ {0x38u, 0x08u},\r
+ {0x39u, 0x40u},\r
+ {0x3Au, 0x02u},\r
{0x3Bu, 0x10u},\r
- {0x3Du, 0x20u},\r
+ {0x3Du, 0x40u},\r
{0x3Eu, 0x04u},\r
- {0x58u, 0x20u},\r
- {0x59u, 0x09u},\r
- {0x5Bu, 0x80u},\r
- {0x61u, 0x80u},\r
- {0x65u, 0x08u},\r
- {0x66u, 0x14u},\r
- {0x67u, 0x04u},\r
- {0x6Cu, 0x20u},\r
- {0x6Fu, 0x06u},\r
- {0x78u, 0x02u},\r
- {0x7Cu, 0x02u},\r
- {0x82u, 0x80u},\r
- {0x85u, 0x40u},\r
- {0x86u, 0x01u},\r
- {0x87u, 0x02u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x80u},\r
- {0x92u, 0x24u},\r
- {0x93u, 0x40u},\r
- {0x95u, 0x40u},\r
- {0x96u, 0x18u},\r
- {0x97u, 0x10u},\r
- {0x98u, 0xCAu},\r
- {0x99u, 0x04u},\r
- {0x9Au, 0x80u},\r
- {0x9Eu, 0x10u},\r
- {0x9Fu, 0x59u},\r
- {0xA0u, 0x0Au},\r
- {0xA1u, 0x14u},\r
- {0xA2u, 0x22u},\r
- {0xA4u, 0xA4u},\r
- {0xA5u, 0x21u},\r
- {0xA7u, 0x08u},\r
- {0xA8u, 0x20u},\r
- {0xB1u, 0x20u},\r
- {0xB5u, 0x04u},\r
- {0xB6u, 0x50u},\r
- {0xC0u, 0x57u},\r
- {0xC2u, 0x3Fu},\r
- {0xC4u, 0x2Cu},\r
- {0xCAu, 0x33u},\r
- {0xCCu, 0x7Fu},\r
- {0xCEu, 0x6Fu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x08u},\r
- {0xDEu, 0x81u},\r
- {0xE2u, 0x01u},\r
- {0xEAu, 0x10u},\r
- {0x87u, 0x11u},\r
- {0x8Bu, 0x06u},\r
- {0x8Fu, 0x01u},\r
- {0x95u, 0x19u},\r
- {0x97u, 0x22u},\r
- {0x99u, 0x08u},\r
- {0xA1u, 0x21u},\r
- {0xA3u, 0x1Cu},\r
- {0xABu, 0x38u},\r
- {0xB3u, 0x38u},\r
- {0xB5u, 0x07u},\r
- {0xD9u, 0x04u},\r
- {0xDCu, 0x10u},\r
- {0xDFu, 0x01u},\r
- {0x04u, 0x04u},\r
- {0x05u, 0x10u},\r
- {0x07u, 0x42u},\r
- {0x0Eu, 0xA2u},\r
- {0x0Fu, 0x08u},\r
- {0x15u, 0x48u},\r
- {0x16u, 0x08u},\r
- {0x17u, 0x11u},\r
- {0x1Eu, 0xA0u},\r
- {0x20u, 0x28u},\r
- {0x21u, 0x10u},\r
- {0x22u, 0x04u},\r
- {0x27u, 0x02u},\r
- {0x28u, 0x88u},\r
- {0x2Fu, 0x1Au},\r
- {0x30u, 0x20u},\r
- {0x32u, 0x04u},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x49u},\r
- {0x39u, 0x20u},\r
- {0x3Bu, 0x44u},\r
- {0x3Du, 0x41u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x18u},\r
- {0x45u, 0x22u},\r
- {0x46u, 0x20u},\r
- {0x47u, 0x08u},\r
- {0x4Du, 0x80u},\r
- {0x4Eu, 0x20u},\r
- {0x4Fu, 0x18u},\r
- {0x56u, 0x55u},\r
- {0x57u, 0x40u},\r
- {0x65u, 0x04u},\r
- {0x66u, 0x50u},\r
- {0x7Cu, 0x02u},\r
- {0x87u, 0x04u},\r
- {0x90u, 0x24u},\r
- {0x91u, 0x88u},\r
- {0x93u, 0x50u},\r
- {0x94u, 0x02u},\r
+ {0x3Fu, 0x11u},\r
+ {0x48u, 0x08u},\r
+ {0x49u, 0x20u},\r
+ {0x60u, 0x02u},\r
+ {0x61u, 0x20u},\r
+ {0x63u, 0xA0u},\r
+ {0x86u, 0x40u},\r
+ {0x88u, 0x01u},\r
+ {0x91u, 0x84u},\r
+ {0x92u, 0x60u},\r
+ {0x93u, 0x05u},\r
{0x95u, 0x41u},\r
- {0x96u, 0x18u},\r
- {0x97u, 0x0Cu},\r
- {0x98u, 0xCAu},\r
- {0x99u, 0x20u},\r
- {0x9Au, 0x80u},\r
- {0x9Bu, 0x08u},\r
- {0x9Du, 0x11u},\r
- {0x9Eu, 0x0Du},\r
- {0x9Fu, 0x11u},\r
- {0xA0u, 0x28u},\r
- {0xA2u, 0x02u},\r
- {0xA4u, 0x94u},\r
- {0xA5u, 0x20u},\r
- {0xA7u, 0x08u},\r
- {0xA8u, 0x20u},\r
- {0xAAu, 0x02u},\r
- {0xAFu, 0x10u},\r
- {0xB7u, 0x04u},\r
- {0xC0u, 0xF0u},\r
- {0xC2u, 0xF0u},\r
- {0xC4u, 0xF0u},\r
- {0xCAu, 0x75u},\r
- {0xCCu, 0xF6u},\r
- {0xCEu, 0xFEu},\r
- {0xD0u, 0xE0u},\r
- {0xD2u, 0x30u},\r
- {0xD8u, 0x70u},\r
- {0xDEu, 0x80u},\r
- {0xEAu, 0x08u},\r
- {0xEEu, 0x10u},\r
- {0x9Eu, 0x40u},\r
- {0x9Fu, 0x08u},\r
- {0xEAu, 0x08u},\r
- {0x9Eu, 0x40u},\r
- {0x9Fu, 0x08u},\r
- {0xABu, 0x01u},\r
- {0xAFu, 0x40u},\r
- {0xB0u, 0x04u},\r
- {0xB3u, 0x40u},\r
- {0xB5u, 0x01u},\r
- {0xB6u, 0x04u},\r
- {0xE2u, 0x01u},\r
- {0xE8u, 0x20u},\r
- {0xEAu, 0x49u},\r
- {0xEEu, 0x40u},\r
- {0x00u, 0x12u},\r
- {0x02u, 0x24u},\r
- {0x05u, 0x02u},\r
- {0x06u, 0x12u},\r
- {0x0Au, 0x0Cu},\r
- {0x0Eu, 0x02u},\r
- {0x11u, 0x06u},\r
- {0x13u, 0x08u},\r
- {0x16u, 0x60u},\r
- {0x17u, 0x0Du},\r
- {0x1Bu, 0x07u},\r
- {0x1Cu, 0x12u},\r
- {0x1Du, 0x07u},\r
- {0x1Eu, 0x48u},\r
- {0x1Fu, 0x08u},\r
- {0x20u, 0x01u},\r
- {0x21u, 0x02u},\r
- {0x25u, 0x01u},\r
- {0x26u, 0x10u},\r
- {0x27u, 0x02u},\r
- {0x29u, 0x10u},\r
- {0x30u, 0x01u},\r
- {0x32u, 0x70u},\r
- {0x33u, 0x08u},\r
- {0x34u, 0x0Eu},\r
- {0x35u, 0x10u},\r
- {0x37u, 0x07u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x14u},\r
- {0x40u, 0x31u},\r
- {0x41u, 0x04u},\r
- {0x42u, 0x60u},\r
- {0x45u, 0xEFu},\r
- {0x46u, 0x20u},\r
- {0x47u, 0xDCu},\r
- {0x48u, 0x3Bu},\r
- {0x49u, 0xFFu},\r
- {0x4Au, 0xFFu},\r
- {0x4Bu, 0xFFu},\r
- {0x4Fu, 0x2Cu},\r
- {0x56u, 0x01u},\r
+ {0x96u, 0x0Cu},\r
+ {0x97u, 0x10u},\r
+ {0x98u, 0x42u},\r
+ {0x99u, 0x06u},\r
+ {0x9Au, 0xC4u},\r
+ {0x9Bu, 0xA0u},\r
+ {0x9Cu, 0x01u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA0u, 0x08u},\r
+ {0xA1u, 0x20u},\r
+ {0xA2u, 0x98u},\r
+ {0xA3u, 0x15u},\r
+ {0xA4u, 0x80u},\r
+ {0xA5u, 0x40u},\r
+ {0xA6u, 0x02u},\r
+ {0xA7u, 0x4Au},\r
+ {0xAAu, 0x10u},\r
+ {0xACu, 0x50u},\r
+ {0xAEu, 0x81u},\r
+ {0xB4u, 0x40u},\r
+ {0xC0u, 0xFFu},\r
+ {0xC2u, 0xF6u},\r
+ {0xC4u, 0xDFu},\r
+ {0xCAu, 0xEFu},\r
+ {0xCCu, 0xFFu},\r
+ {0xCEu, 0xFFu},\r
+ {0xD8u, 0x0Fu},\r
+ {0xE2u, 0x09u},\r
+ {0xE6u, 0x08u},\r
+ {0xEAu, 0x02u},\r
+ {0xECu, 0x04u},\r
+ {0x38u, 0x80u},\r
+ {0x3Eu, 0x40u},\r
+ {0x58u, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x1Fu, 0x80u},\r
+ {0x8Au, 0x04u},\r
+ {0x92u, 0x0Cu},\r
+ {0x97u, 0x01u},\r
+ {0x9Bu, 0x80u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Du, 0x20u},\r
+ {0xA3u, 0x08u},\r
+ {0xAAu, 0x04u},\r
+ {0xADu, 0x40u},\r
+ {0xB5u, 0x08u},\r
+ {0xE2u, 0x09u},\r
+ {0xE6u, 0x28u},\r
+ {0xE8u, 0x40u},\r
+ {0x92u, 0x0Cu},\r
+ {0x97u, 0x01u},\r
+ {0x9Bu, 0x80u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Du, 0x28u},\r
+ {0xA1u, 0x40u},\r
+ {0xA3u, 0x08u},\r
+ {0xA6u, 0x04u},\r
+ {0xA8u, 0x40u},\r
+ {0xA9u, 0x04u},\r
+ {0xAEu, 0x04u},\r
+ {0xB0u, 0x20u},\r
+ {0xB1u, 0x01u},\r
+ {0xB6u, 0x08u},\r
+ {0xB7u, 0x08u},\r
+ {0xE0u, 0x20u},\r
+ {0xEAu, 0x94u},\r
+ {0xEEu, 0xA4u},\r
+ {0x01u, 0x0Fu},\r
+ {0x03u, 0xF0u},\r
+ {0x04u, 0x50u},\r
+ {0x05u, 0x30u},\r
+ {0x06u, 0xA0u},\r
+ {0x07u, 0xC0u},\r
+ {0x08u, 0x06u},\r
+ {0x09u, 0x50u},\r
+ {0x0Au, 0x09u},\r
+ {0x0Bu, 0xA0u},\r
+ {0x0Cu, 0x03u},\r
+ {0x0Du, 0x60u},\r
+ {0x0Eu, 0x0Cu},\r
+ {0x0Fu, 0x90u},\r
+ {0x11u, 0xFFu},\r
+ {0x12u, 0xFFu},\r
+ {0x14u, 0xFFu},\r
+ {0x15u, 0x05u},\r
+ {0x17u, 0x0Au},\r
+ {0x18u, 0x05u},\r
+ {0x19u, 0x06u},\r
+ {0x1Au, 0x0Au},\r
+ {0x1Bu, 0x09u},\r
+ {0x1Cu, 0x0Fu},\r
+ {0x1Eu, 0xF0u},\r
+ {0x1Fu, 0xFFu},\r
+ {0x21u, 0x03u},\r
+ {0x22u, 0xFFu},\r
+ {0x23u, 0x0Cu},\r
+ {0x24u, 0x30u},\r
+ {0x26u, 0xC0u},\r
+ {0x27u, 0xFFu},\r
+ {0x2Cu, 0x60u},\r
+ {0x2Eu, 0x90u},\r
+ {0x35u, 0xFFu},\r
+ {0x36u, 0xFFu},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x10u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
- {0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
- {0x62u, 0xC0u},\r
- {0x66u, 0x80u},\r
- {0x68u, 0x40u},\r
- {0x69u, 0x40u},\r
- {0x6Eu, 0x08u},\r
- {0x81u, 0x02u},\r
- {0x84u, 0x02u},\r
- {0x89u, 0x01u},\r
- {0x8Du, 0x04u},\r
- {0xACu, 0x01u},\r
- {0xB3u, 0x01u},\r
- {0xB4u, 0x02u},\r
- {0xB5u, 0x02u},\r
- {0xB6u, 0x01u},\r
- {0xB7u, 0x04u},\r
- {0xBEu, 0x50u},\r
- {0xBFu, 0x54u},\r
+ {0x84u, 0x10u},\r
+ {0x86u, 0x09u},\r
+ {0x87u, 0x10u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Du, 0x0Au},\r
+ {0x8Fu, 0x14u},\r
+ {0x90u, 0x08u},\r
+ {0x92u, 0x10u},\r
+ {0x93u, 0x04u},\r
+ {0x94u, 0x04u},\r
+ {0x95u, 0x01u},\r
+ {0x9Cu, 0x19u},\r
+ {0x9Eu, 0x62u},\r
+ {0xA0u, 0x40u},\r
+ {0xA2u, 0x22u},\r
+ {0xABu, 0x02u},\r
+ {0xACu, 0x20u},\r
+ {0xAEu, 0x40u},\r
+ {0xB0u, 0x04u},\r
+ {0xB1u, 0x06u},\r
+ {0xB2u, 0x03u},\r
+ {0xB3u, 0x18u},\r
+ {0xB4u, 0x78u},\r
+ {0xB5u, 0x01u},\r
+ {0xBEu, 0x15u},\r
+ {0xBFu, 0x15u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
{0x01u, 0x08u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x60u},\r
- {0x07u, 0x01u},\r
- {0x08u, 0x08u},\r
- {0x09u, 0x08u},\r
- {0x0Du, 0x80u},\r
- {0x0Eu, 0x20u},\r
- {0x10u, 0x10u},\r
- {0x12u, 0x22u},\r
+ {0x04u, 0x08u},\r
+ {0x05u, 0x20u},\r
+ {0x06u, 0x02u},\r
+ {0x09u, 0x06u},\r
+ {0x0Bu, 0x01u},\r
+ {0x0Cu, 0x01u},\r
+ {0x0Du, 0x50u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x21u},\r
+ {0x11u, 0x02u},\r
+ {0x12u, 0x01u},\r
{0x14u, 0x80u},\r
- {0x17u, 0x04u},\r
- {0x19u, 0xA0u},\r
- {0x1Cu, 0x40u},\r
- {0x1Du, 0x10u},\r
- {0x1Eu, 0x20u},\r
- {0x20u, 0x01u},\r
- {0x21u, 0x08u},\r
- {0x23u, 0x04u},\r
- {0x25u, 0x80u},\r
- {0x26u, 0xA8u},\r
- {0x2Cu, 0x04u},\r
- {0x2Du, 0x02u},\r
+ {0x15u, 0x44u},\r
+ {0x18u, 0xA0u},\r
+ {0x1Au, 0x08u},\r
+ {0x1Bu, 0x30u},\r
+ {0x1Fu, 0x80u},\r
+ {0x22u, 0x2Au},\r
+ {0x27u, 0x08u},\r
+ {0x29u, 0x20u},\r
{0x2Eu, 0x02u},\r
- {0x2Fu, 0x10u},\r
- {0x34u, 0x20u},\r
- {0x36u, 0x80u},\r
- {0x37u, 0x0Au},\r
- {0x39u, 0x20u},\r
- {0x3Bu, 0x81u},\r
+ {0x2Fu, 0x20u},\r
+ {0x31u, 0x08u},\r
+ {0x33u, 0x02u},\r
+ {0x34u, 0x83u},\r
+ {0x35u, 0x20u},\r
+ {0x36u, 0x04u},\r
+ {0x38u, 0x08u},\r
+ {0x39u, 0xA0u},\r
+ {0x3Du, 0x91u},\r
{0x3Eu, 0x04u},\r
- {0x3Fu, 0x08u},\r
- {0x45u, 0x80u},\r
- {0x46u, 0x60u},\r
- {0x47u, 0x0Au},\r
- {0x4Eu, 0x58u},\r
- {0x55u, 0x10u},\r
- {0x56u, 0x02u},\r
- {0x57u, 0x04u},\r
- {0x59u, 0x02u},\r
- {0x5Au, 0xA4u},\r
- {0x5Cu, 0x49u},\r
- {0x5Du, 0x20u},\r
- {0x64u, 0x10u},\r
- {0x65u, 0x80u},\r
- {0x67u, 0x44u},\r
- {0x6Eu, 0x08u},\r
- {0x6Fu, 0x45u},\r
- {0x74u, 0xA4u},\r
- {0x75u, 0x01u},\r
- {0x81u, 0x10u},\r
- {0x82u, 0x02u},\r
- {0x83u, 0x40u},\r
- {0x84u, 0xA0u},\r
- {0x85u, 0x80u},\r
- {0x88u, 0x04u},\r
- {0x89u, 0x10u},\r
- {0x8Au, 0x10u},\r
- {0x8Du, 0x18u},\r
- {0x93u, 0x20u},\r
- {0x98u, 0xA0u},\r
- {0xB0u, 0x80u},\r
- {0xC0u, 0xF4u},\r
- {0xC2u, 0xA0u},\r
- {0xC4u, 0x31u},\r
- {0xCAu, 0xE0u},\r
- {0xCCu, 0xF0u},\r
- {0xCEu, 0x4Du},\r
- {0xD0u, 0xD0u},\r
- {0xD2u, 0x20u},\r
- {0xD6u, 0xFFu},\r
- {0xD8u, 0xF0u},\r
- {0xE2u, 0xA1u},\r
- {0xE6u, 0x90u},\r
- {0xE8u, 0x42u},\r
- {0xEAu, 0x08u},\r
- {0xECu, 0x08u},\r
- {0x80u, 0x20u},\r
- {0x87u, 0x10u},\r
- {0xE0u, 0x80u},\r
- {0xE6u, 0x07u},\r
- {0xB4u, 0x04u},\r
- {0x00u, 0xD6u},\r
- {0x04u, 0xD2u},\r
- {0x05u, 0x40u},\r
- {0x06u, 0x04u},\r
- {0x07u, 0x30u},\r
- {0x08u, 0x29u},\r
- {0x09u, 0x58u},\r
- {0x0Au, 0x16u},\r
- {0x0Bu, 0x23u},\r
- {0x0Cu, 0x04u},\r
- {0x0Fu, 0x0Cu},\r
- {0x12u, 0x80u},\r
- {0x14u, 0x31u},\r
- {0x16u, 0x0Eu},\r
- {0x17u, 0x01u},\r
- {0x1Bu, 0x82u},\r
- {0x1Cu, 0x22u},\r
- {0x1Eu, 0x10u},\r
- {0x20u, 0xD6u},\r
- {0x24u, 0x17u},\r
- {0x25u, 0x34u},\r
- {0x26u, 0x28u},\r
- {0x27u, 0x43u},\r
- {0x28u, 0xD0u},\r
- {0x29u, 0x11u},\r
- {0x2Au, 0x06u},\r
- {0x2Bu, 0x62u},\r
- {0x2Cu, 0x06u},\r
- {0x2Eu, 0xD0u},\r
- {0x30u, 0x40u},\r
- {0x32u, 0x80u},\r
- {0x33u, 0x80u},\r
- {0x34u, 0x0Fu},\r
- {0x35u, 0x70u},\r
- {0x36u, 0x30u},\r
- {0x37u, 0x0Fu},\r
- {0x38u, 0x20u},\r
- {0x39u, 0x02u},\r
- {0x3Au, 0x80u},\r
- {0x3Bu, 0x20u},\r
- {0x3Eu, 0x05u},\r
{0x3Fu, 0x01u},\r
+ {0x6Cu, 0x04u},\r
+ {0x6Du, 0xD6u},\r
+ {0x6Eu, 0x04u},\r
+ {0x6Fu, 0x0Au},\r
+ {0x74u, 0x20u},\r
+ {0x75u, 0x80u},\r
+ {0x76u, 0x11u},\r
+ {0x77u, 0x80u},\r
+ {0x82u, 0x20u},\r
+ {0x86u, 0x02u},\r
+ {0x88u, 0x80u},\r
+ {0x89u, 0x02u},\r
+ {0x8Au, 0x02u},\r
+ {0x8Cu, 0x10u},\r
+ {0x8Fu, 0x80u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Du, 0xA0u},\r
+ {0x9Eu, 0x10u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA1u, 0x08u},\r
+ {0xA7u, 0x10u},\r
+ {0xAEu, 0x10u},\r
+ {0xB1u, 0x80u},\r
+ {0xB7u, 0x10u},\r
+ {0xC0u, 0xE4u},\r
+ {0xC2u, 0xFDu},\r
+ {0xC4u, 0xB9u},\r
+ {0xCAu, 0xC4u},\r
+ {0xCCu, 0xF3u},\r
+ {0xCEu, 0xFEu},\r
+ {0xE0u, 0xA2u},\r
+ {0xE2u, 0x50u},\r
+ {0xE4u, 0x20u},\r
+ {0xE6u, 0x98u},\r
+ {0xEAu, 0x14u},\r
+ {0xEEu, 0x82u},\r
+ {0x85u, 0x20u},\r
+ {0x87u, 0x08u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Du, 0x08u},\r
+ {0xE2u, 0x10u},\r
+ {0xAFu, 0x10u},\r
+ {0xB2u, 0x20u},\r
+ {0xB4u, 0x40u},\r
+ {0xEAu, 0x40u},\r
+ {0xECu, 0x02u},\r
+ {0x00u, 0x03u},\r
+ {0x02u, 0x0Cu},\r
+ {0x04u, 0x60u},\r
+ {0x05u, 0x01u},\r
+ {0x06u, 0x90u},\r
+ {0x07u, 0x02u},\r
+ {0x0Bu, 0x10u},\r
+ {0x0Cu, 0x0Fu},\r
+ {0x0Eu, 0xF0u},\r
+ {0x11u, 0x08u},\r
+ {0x13u, 0x10u},\r
+ {0x14u, 0x05u},\r
+ {0x16u, 0x0Au},\r
+ {0x17u, 0x01u},\r
+ {0x18u, 0x06u},\r
+ {0x1Au, 0x09u},\r
+ {0x1Bu, 0x06u},\r
+ {0x1Fu, 0x08u},\r
+ {0x20u, 0x50u},\r
+ {0x21u, 0x01u},\r
+ {0x22u, 0xA0u},\r
+ {0x23u, 0x04u},\r
+ {0x24u, 0x30u},\r
+ {0x26u, 0xC0u},\r
+ {0x2Fu, 0x01u},\r
+ {0x34u, 0xFFu},\r
+ {0x35u, 0x07u},\r
+ {0x37u, 0x18u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x40u},\r
{0x56u, 0x02u},\r
{0x57u, 0x28u},\r
- {0x58u, 0x0Bu},\r
- {0x59u, 0x0Bu},\r
- {0x5Bu, 0x0Bu},\r
- {0x5Cu, 0x99u},\r
- {0x5Du, 0x90u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x05u},\r
- {0x86u, 0x0Au},\r
- {0x87u, 0x70u},\r
- {0x88u, 0x03u},\r
- {0x8Au, 0x0Cu},\r
- {0x8Bu, 0x80u},\r
- {0x8Cu, 0x30u},\r
- {0x8Eu, 0xC0u},\r
- {0x8Fu, 0x04u},\r
- {0x95u, 0x09u},\r
- {0x97u, 0x14u},\r
- {0x98u, 0x06u},\r
- {0x99u, 0x01u},\r
- {0x9Au, 0x09u},\r
+ {0x86u, 0xECu},\r
+ {0x87u, 0xFFu},\r
+ {0x8Bu, 0xFFu},\r
+ {0x8Du, 0x0Fu},\r
+ {0x8Eu, 0x01u},\r
+ {0x8Fu, 0xF0u},\r
+ {0x91u, 0x30u},\r
+ {0x93u, 0xC0u},\r
+ {0x98u, 0x04u},\r
+ {0x99u, 0x05u},\r
+ {0x9Au, 0x43u},\r
{0x9Bu, 0x0Au},\r
- {0x9Du, 0x40u},\r
- {0x9Fu, 0x80u},\r
- {0xA0u, 0x0Fu},\r
- {0xA1u, 0x0Eu},\r
- {0xA2u, 0xF0u},\r
- {0xA3u, 0x21u},\r
- {0xA4u, 0x60u},\r
- {0xA6u, 0x90u},\r
- {0xA8u, 0x50u},\r
- {0xAAu, 0xA0u},\r
- {0xABu, 0x07u},\r
- {0xAFu, 0x08u},\r
- {0xB1u, 0xC0u},\r
- {0xB2u, 0xFFu},\r
- {0xB3u, 0x38u},\r
- {0xB5u, 0x07u},\r
- {0xBEu, 0x04u},\r
- {0xBFu, 0x01u},\r
+ {0x9Du, 0x03u},\r
+ {0x9Eu, 0x12u},\r
+ {0x9Fu, 0x0Cu},\r
+ {0xA0u, 0xE0u},\r
+ {0xA1u, 0x50u},\r
+ {0xA3u, 0xA0u},\r
+ {0xA7u, 0xFFu},\r
+ {0xA8u, 0x88u},\r
+ {0xA9u, 0x09u},\r
+ {0xAAu, 0x03u},\r
+ {0xABu, 0x06u},\r
+ {0xACu, 0x21u},\r
+ {0xADu, 0x90u},\r
+ {0xAEu, 0x02u},\r
+ {0xAFu, 0x60u},\r
+ {0xB0u, 0xE0u},\r
+ {0xB3u, 0xFFu},\r
+ {0xB4u, 0x0Fu},\r
+ {0xB6u, 0x10u},\r
+ {0xBEu, 0x01u},\r
+ {0xBFu, 0x04u},\r
+ {0xD4u, 0x09u},\r
+ {0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x10u},\r
+ {0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x08u},\r
- {0x01u, 0x20u},\r
- {0x02u, 0x02u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x01u},\r
- {0x07u, 0x50u},\r
- {0x0Bu, 0x08u},\r
- {0x0Eu, 0x02u},\r
- {0x0Fu, 0x90u},\r
- {0x10u, 0x48u},\r
- {0x12u, 0x10u},\r
- {0x15u, 0x50u},\r
- {0x17u, 0x09u},\r
- {0x1Au, 0x10u},\r
- {0x1Du, 0x37u},\r
- {0x1Eu, 0x03u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x80u},\r
+ {0x07u, 0xA2u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Bu, 0x01u},\r
+ {0x0Eu, 0x20u},\r
+ {0x0Fu, 0x08u},\r
+ {0x10u, 0x40u},\r
+ {0x12u, 0x02u},\r
+ {0x13u, 0x10u},\r
+ {0x16u, 0x60u},\r
+ {0x18u, 0x44u},\r
+ {0x19u, 0x80u},\r
{0x1Fu, 0x10u},\r
- {0x20u, 0x04u},\r
- {0x21u, 0x05u},\r
- {0x22u, 0x10u},\r
- {0x23u, 0x04u},\r
- {0x24u, 0x02u},\r
- {0x25u, 0x51u},\r
- {0x26u, 0x08u},\r
- {0x28u, 0x88u},\r
+ {0x22u, 0x04u},\r
+ {0x25u, 0x40u},\r
+ {0x26u, 0x20u},\r
+ {0x28u, 0xA0u},\r
+ {0x29u, 0x10u},\r
{0x2Au, 0x80u},\r
- {0x2Eu, 0x20u},\r
- {0x2Fu, 0x10u},\r
- {0x30u, 0x40u},\r
- {0x32u, 0x14u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Eu, 0x40u},\r
+ {0x30u, 0x01u},\r
+ {0x32u, 0x90u},\r
+ {0x35u, 0x10u},\r
{0x36u, 0x28u},\r
- {0x38u, 0x20u},\r
- {0x39u, 0x88u},\r
- {0x3Au, 0x10u},\r
- {0x3Bu, 0x08u},\r
- {0x3Du, 0x80u},\r
- {0x3Eu, 0x08u},\r
- {0x3Fu, 0x10u},\r
- {0x45u, 0x10u},\r
- {0x46u, 0x08u},\r
- {0x66u, 0x08u},\r
- {0x6Cu, 0x80u},\r
- {0x6Du, 0x50u},\r
- {0x6Fu, 0x58u},\r
- {0x77u, 0x01u},\r
- {0x7Cu, 0x02u},\r
- {0x83u, 0x12u},\r
- {0x8Du, 0x01u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x80u},\r
- {0x92u, 0x08u},\r
- {0x93u, 0x10u},\r
- {0x94u, 0x02u},\r
- {0x95u, 0x42u},\r
- {0x96u, 0x11u},\r
- {0x97u, 0x24u},\r
- {0x98u, 0xCAu},\r
- {0x99u, 0x20u},\r
- {0x9Au, 0xA1u},\r
- {0x9Bu, 0x08u},\r
- {0x9Du, 0x15u},\r
+ {0x37u, 0x82u},\r
+ {0x39u, 0x84u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Du, 0x20u},\r
+ {0x3Eu, 0x20u},\r
+ {0x3Fu, 0x04u},\r
+ {0x59u, 0x25u},\r
+ {0x5Au, 0x80u},\r
+ {0x63u, 0x82u},\r
+ {0x66u, 0x04u},\r
+ {0x69u, 0x80u},\r
+ {0x6Bu, 0x02u},\r
+ {0x6Cu, 0x20u},\r
+ {0x6Du, 0x41u},\r
+ {0x6Fu, 0xD9u},\r
+ {0x74u, 0x80u},\r
+ {0x76u, 0x02u},\r
+ {0x81u, 0x40u},\r
+ {0x8Fu, 0x40u},\r
+ {0x91u, 0x04u},\r
+ {0x92u, 0xE4u},\r
+ {0x93u, 0x15u},\r
+ {0x95u, 0x41u},\r
+ {0x96u, 0x08u},\r
+ {0x98u, 0xE1u},\r
+ {0x99u, 0x27u},\r
+ {0x9Au, 0xC4u},\r
+ {0x9Bu, 0xA0u},\r
+ {0x9Eu, 0x02u},\r
{0x9Fu, 0x51u},\r
- {0xA0u, 0x0Cu},\r
- {0xA2u, 0x22u},\r
- {0xA3u, 0x40u},\r
- {0xA4u, 0x80u},\r
- {0xA5u, 0x22u},\r
- {0xA6u, 0x01u},\r
- {0xA7u, 0x0Au},\r
- {0xB0u, 0x10u},\r
- {0xB1u, 0x01u},\r
- {0xB5u, 0x80u},\r
- {0xC0u, 0xF7u},\r
- {0xC2u, 0xB2u},\r
- {0xC4u, 0xFEu},\r
- {0xCAu, 0x6Du},\r
- {0xCCu, 0x6Eu},\r
- {0xCEu, 0x7Eu},\r
- {0xD8u, 0x40u},\r
- {0xDEu, 0x80u},\r
- {0xE2u, 0x10u},\r
- {0xEAu, 0x20u},\r
- {0xECu, 0x40u},\r
- {0x9Fu, 0x08u},\r
- {0xB2u, 0x40u},\r
- {0xECu, 0x80u},\r
- {0xB7u, 0x08u},\r
- {0xECu, 0x40u},\r
- {0x30u, 0x20u},\r
- {0x33u, 0x02u},\r
- {0x34u, 0x04u},\r
- {0x35u, 0x20u},\r
- {0x38u, 0x80u},\r
- {0x56u, 0x80u},\r
- {0x5Bu, 0x02u},\r
- {0x5Eu, 0x01u},\r
- {0x63u, 0x40u},\r
- {0x65u, 0x04u},\r
- {0x81u, 0x20u},\r
- {0x8Du, 0x04u},\r
- {0xCCu, 0xF0u},\r
- {0xCEu, 0x10u},\r
- {0xD4u, 0x40u},\r
+ {0xA1u, 0x10u},\r
+ {0xA2u, 0x9Au},\r
+ {0xA3u, 0x05u},\r
+ {0xA4u, 0xA0u},\r
+ {0xA5u, 0x40u},\r
+ {0xA7u, 0x88u},\r
+ {0xB0u, 0xA0u},\r
+ {0xB5u, 0x10u},\r
+ {0xC0u, 0xB5u},\r
+ {0xC2u, 0x63u},\r
+ {0xC4u, 0x3Bu},\r
+ {0xCAu, 0x9Fu},\r
+ {0xCCu, 0xFDu},\r
+ {0xCEu, 0x6Eu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x49u},\r
+ {0xE0u, 0x01u},\r
+ {0xE6u, 0x40u},\r
+ {0xEEu, 0x06u},\r
+ {0x83u, 0x01u},\r
+ {0x97u, 0x01u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Du, 0x20u},\r
+ {0xABu, 0x80u},\r
+ {0xB2u, 0x04u},\r
+ {0xB3u, 0x08u},\r
+ {0xB7u, 0x80u},\r
+ {0xEAu, 0xA0u},\r
+ {0xEEu, 0x12u},\r
+ {0xACu, 0x02u},\r
+ {0xB1u, 0x20u},\r
+ {0xE8u, 0x20u},\r
+ {0x12u, 0x08u},\r
+ {0x15u, 0x80u},\r
+ {0x17u, 0x01u},\r
+ {0x33u, 0x01u},\r
+ {0x36u, 0x88u},\r
+ {0x38u, 0x01u},\r
+ {0x39u, 0x80u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Du, 0x80u},\r
+ {0x43u, 0x10u},\r
+ {0x50u, 0x80u},\r
+ {0x5Au, 0x04u},\r
+ {0x5Du, 0x02u},\r
+ {0x61u, 0x20u},\r
+ {0x64u, 0x08u},\r
+ {0x89u, 0x40u},\r
+ {0x8Cu, 0x01u},\r
+ {0x8Du, 0x20u},\r
+ {0xC4u, 0xE0u},\r
+ {0xCCu, 0xE0u},\r
+ {0xCEu, 0xF0u},\r
+ {0xD0u, 0x10u},\r
+ {0xD4u, 0x20u},\r
{0xD6u, 0xC0u},\r
{0xD8u, 0xC0u},\r
- {0xE6u, 0x80u},\r
- {0x51u, 0x02u},\r
- {0x56u, 0x20u},\r
- {0x5Eu, 0x01u},\r
- {0x5Fu, 0x20u},\r
- {0x8Eu, 0x20u},\r
- {0x94u, 0x80u},\r
- {0x97u, 0x40u},\r
- {0x9Cu, 0x04u},\r
- {0x9Eu, 0x80u},\r
- {0x9Fu, 0x02u},\r
- {0xA4u, 0x20u},\r
- {0xAFu, 0x02u},\r
- {0xB2u, 0x01u},\r
- {0xD4u, 0xC0u},\r
- {0xD6u, 0xA0u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x04u},\r
+ {0x36u, 0x40u},\r
+ {0x37u, 0x04u},\r
+ {0x50u, 0x08u},\r
+ {0x51u, 0x01u},\r
+ {0x55u, 0x08u},\r
+ {0x5Du, 0x02u},\r
+ {0x81u, 0x02u},\r
+ {0x89u, 0x01u},\r
+ {0x94u, 0x04u},\r
+ {0x96u, 0x04u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA6u, 0x80u},\r
+ {0xACu, 0x80u},\r
+ {0xADu, 0x02u},\r
+ {0xCCu, 0xF0u},\r
+ {0xD4u, 0xE0u},\r
+ {0xD6u, 0x80u},\r
+ {0xE6u, 0x20u},\r
{0xEAu, 0x10u},\r
- {0x10u, 0x20u},\r
- {0x80u, 0x40u},\r
- {0x83u, 0x80u},\r
- {0x86u, 0x81u},\r
- {0x87u, 0x02u},\r
- {0x94u, 0x80u},\r
- {0x96u, 0x01u},\r
- {0x97u, 0x40u},\r
- {0x9Bu, 0x40u},\r
- {0x9Cu, 0x04u},\r
- {0x9Eu, 0x80u},\r
- {0x9Fu, 0x02u},\r
- {0xA4u, 0x20u},\r
- {0xA5u, 0x02u},\r
- {0xABu, 0x20u},\r
- {0xB7u, 0x40u},\r
+ {0xEEu, 0x10u},\r
+ {0x12u, 0x80u},\r
+ {0x80u, 0x08u},\r
+ {0x86u, 0x04u},\r
+ {0x89u, 0x02u},\r
+ {0x8Cu, 0x08u},\r
+ {0x96u, 0x0Cu},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Fu, 0x14u},\r
+ {0xA4u, 0x08u},\r
+ {0xA5u, 0x20u},\r
+ {0xA6u, 0xC0u},\r
+ {0xB4u, 0x04u},\r
+ {0xB5u, 0x08u},\r
{0xC4u, 0x10u},\r
- {0xE2u, 0xD0u},\r
- {0xE4u, 0x20u},\r
- {0xE6u, 0x40u},\r
- {0xEAu, 0x80u},\r
- {0x86u, 0x80u},\r
- {0x97u, 0x40u},\r
- {0x9Bu, 0x40u},\r
- {0xA1u, 0x80u},\r
- {0xA7u, 0x80u},\r
- {0xACu, 0x04u},\r
- {0xADu, 0x80u},\r
- {0xB5u, 0x02u},\r
- {0xE4u, 0x10u},\r
- {0xEAu, 0x10u},\r
- {0xEEu, 0x40u},\r
- {0x0Bu, 0x02u},\r
- {0x0Fu, 0x40u},\r
- {0x10u, 0x10u},\r
- {0x52u, 0x80u},\r
- {0x54u, 0x40u},\r
- {0x58u, 0x20u},\r
- {0x5Eu, 0x20u},\r
- {0x80u, 0x02u},\r
- {0x83u, 0x01u},\r
- {0x87u, 0x40u},\r
- {0x88u, 0x20u},\r
+ {0xE2u, 0xC0u},\r
+ {0x63u, 0x08u},\r
+ {0x83u, 0x04u},\r
+ {0x85u, 0x20u},\r
+ {0x86u, 0x04u},\r
+ {0x87u, 0x08u},\r
+ {0x96u, 0x08u},\r
+ {0x9Du, 0x02u},\r
+ {0x9Fu, 0x14u},\r
+ {0xA5u, 0x20u},\r
+ {0xA6u, 0x40u},\r
+ {0xD8u, 0x40u},\r
+ {0xE2u, 0x90u},\r
+ {0xE6u, 0x50u},\r
+ {0x09u, 0x80u},\r
+ {0x0Eu, 0x80u},\r
+ {0x13u, 0x01u},\r
+ {0x50u, 0x80u},\r
+ {0x51u, 0x02u},\r
+ {0x54u, 0x04u},\r
+ {0x56u, 0x01u},\r
+ {0x8Fu, 0x01u},\r
{0xC2u, 0x06u},\r
{0xC4u, 0x08u},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0xE0u, 0x01u},\r
- {0x00u, 0x20u},\r
- {0x06u, 0x40u},\r
- {0x07u, 0x04u},\r
- {0x09u, 0x02u},\r
- {0x0Bu, 0x04u},\r
+ {0xE6u, 0x08u},\r
+ {0x02u, 0x08u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x20u},\r
+ {0x08u, 0x24u},\r
+ {0x0Du, 0x08u},\r
{0x0Eu, 0x08u},\r
- {0x0Fu, 0x10u},\r
- {0x81u, 0x02u},\r
- {0x8Au, 0x40u},\r
- {0x8Bu, 0x04u},\r
- {0x8Eu, 0x04u},\r
- {0x9Cu, 0x02u},\r
- {0xA4u, 0x02u},\r
- {0xACu, 0x42u},\r
- {0xAEu, 0x10u},\r
- {0xB0u, 0x10u},\r
- {0xB6u, 0x80u},\r
+ {0x84u, 0x20u},\r
+ {0x85u, 0x02u},\r
+ {0x88u, 0x04u},\r
+ {0x8Cu, 0x80u},\r
+ {0x8Du, 0x88u},\r
+ {0x9Eu, 0x21u},\r
+ {0xA1u, 0x80u},\r
+ {0xA4u, 0x84u},\r
+ {0xA5u, 0x02u},\r
+ {0xAAu, 0x20u},\r
+ {0xAEu, 0x40u},\r
{0xC0u, 0x07u},\r
{0xC2u, 0x0Fu},\r
- {0xE2u, 0x02u},\r
- {0xE6u, 0x05u},\r
- {0xE8u, 0x02u},\r
- {0xEAu, 0x04u},\r
- {0x81u, 0x40u},\r
- {0x9Cu, 0x02u},\r
- {0xA4u, 0x02u},\r
- {0xABu, 0x04u},\r
- {0xAFu, 0x10u},\r
- {0xB0u, 0x10u},\r
- {0xEEu, 0x01u},\r
- {0x08u, 0x02u},\r
- {0x0Au, 0x01u},\r
- {0x0Cu, 0x02u},\r
- {0x0Du, 0x40u},\r
- {0x95u, 0x80u},\r
- {0x96u, 0x01u},\r
- {0x9Cu, 0x02u},\r
- {0xA4u, 0x02u},\r
- {0xAEu, 0x01u},\r
+ {0xE2u, 0x08u},\r
+ {0xE4u, 0x02u},\r
+ {0xE6u, 0x09u},\r
+ {0x88u, 0x04u},\r
+ {0xA4u, 0x04u},\r
+ {0xAAu, 0x0Cu},\r
+ {0xB1u, 0x40u},\r
+ {0xB6u, 0x01u},\r
+ {0xE0u, 0x04u},\r
+ {0xEAu, 0x01u},\r
+ {0xECu, 0x02u},\r
+ {0x0Bu, 0x88u},\r
+ {0x0Fu, 0x41u},\r
+ {0x83u, 0x01u},\r
+ {0x87u, 0x44u},\r
{0xC2u, 0x0Fu},\r
- {0x26u, 0x80u},\r
- {0x65u, 0x04u},\r
- {0x8Du, 0x04u},\r
- {0x9Bu, 0x40u},\r
+ {0x8Fu, 0x10u},\r
+ {0x9Du, 0x02u},\r
{0x9Fu, 0x10u},\r
- {0xA1u, 0x80u},\r
- {0xA6u, 0x80u},\r
- {0xA7u, 0x80u},\r
- {0xB3u, 0x40u},\r
- {0xB7u, 0x10u},\r
- {0xC8u, 0x20u},\r
- {0xD8u, 0x80u},\r
- {0x07u, 0x10u},\r
- {0x1Bu, 0x80u},\r
- {0x51u, 0x80u},\r
- {0x5Bu, 0x40u},\r
- {0x9Bu, 0x40u},\r
- {0x9Fu, 0x10u},\r
- {0xA1u, 0x80u},\r
- {0xA7u, 0x80u},\r
+ {0xA3u, 0x08u},\r
+ {0xABu, 0x04u},\r
+ {0xAEu, 0x40u},\r
+ {0xEEu, 0x60u},\r
+ {0x05u, 0x02u},\r
+ {0x57u, 0x08u},\r
+ {0x5Du, 0x40u},\r
+ {0x91u, 0x40u},\r
+ {0x9Du, 0x02u},\r
+ {0xA3u, 0x08u},\r
+ {0xB5u, 0x40u},\r
{0xC0u, 0x20u},\r
- {0xC6u, 0x40u},\r
- {0xD4u, 0xA0u},\r
- {0x00u, 0x02u},\r
- {0x01u, 0x01u},\r
- {0x08u, 0x02u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0x02u},\r
- {0x0Bu, 0x01u},\r
- {0x0Eu, 0x02u},\r
- {0x10u, 0x02u},\r
- {0x11u, 0x01u},\r
- {0x1Au, 0x02u},\r
- {0x1Bu, 0x01u},\r
- {0x00u, 0xABu},\r
- {0x01u, 0x02u},\r
+ {0xD4u, 0x40u},\r
+ {0xD6u, 0x20u},\r
+ {0xAFu, 0x40u},\r
+ {0x00u, 0x03u},\r
+ {0x08u, 0x03u},\r
+ {0x0Au, 0x03u},\r
+ {0x10u, 0x03u},\r
+ {0x1Au, 0x03u},\r
+ {0x00u, 0xFDu},\r
+ {0x01u, 0xABu},\r
+ {0x02u, 0x02u},\r
+ {0x10u, 0x55u},\r
};\r
\r
\r
/* address, size */\r
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1024u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P2_U1_BASE), 2944u},\r
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},\r
};\r
\r
- /* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */\r
- static const uint8 CYCODE BS_UDB_1_2_1_CONFIG_VAL[] = {\r
- 0x01u, 0x80u, 0x00u, 0x00u, 0x07u, 0x00u, 0x18u, 0x9Fu, 0x08u, 0x7Fu, 0x21u, 0x80u, 0x40u, 0x90u, 0x00u, 0x40u, \r
- 0x40u, 0xC0u, 0x00u, 0x01u, 0x04u, 0x1Fu, 0x00u, 0x20u, 0x10u, 0x00u, 0x00u, 0x60u, 0x01u, 0xC0u, 0x00u, 0x02u, \r
- 0x01u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x08u, 0xFFu, 0x01u, 0xC0u, 0x00u, 0x08u, 0x01u, 0xC0u, 0x00u, 0x04u, \r
- 0x3Fu, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x0Au, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, \r
- 0x26u, 0x03u, 0x40u, 0x00u, 0x05u, 0x0Bu, 0xFDu, 0xCEu, 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x0Bu, 0x04u, 0x0Bu, 0x0Bu, 0x09u, 0x99u, 0x00u, 0x01u, \r
+ /* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */\r
+ static const uint8 CYCODE BS_UDB_1_3_0_CONFIG_VAL[] = {\r
+ 0x8Du, 0x00u, 0x00u, 0x00u, 0x8Du, 0x09u, 0x00u, 0x12u, 0x8Du, 0x00u, 0x00u, 0x01u, 0x0Du, 0x00u, 0x80u, 0x30u, \r
+ 0x02u, 0x00u, 0x0Du, 0x00u, 0x00u, 0x00u, 0x80u, 0x09u, 0x12u, 0x00u, 0x44u, 0x06u, 0x60u, 0x00u, 0x00u, 0x08u, \r
+ 0x8Du, 0x09u, 0x00u, 0x24u, 0x00u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x18u, 0x00u, 0x11u, 0x00u, 0x22u, 0x00u, \r
+ 0x0Fu, 0x38u, 0x00u, 0x00u, 0x80u, 0x07u, 0x70u, 0x00u, 0x80u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, \r
+ 0x26u, 0x05u, 0x40u, 0x00u, 0x03u, 0xBEu, 0xFBu, 0xDCu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x10u, 0x00u, 0x00u, 0x01u, \r
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P3_U0_BASE), BS_UDB_1_2_1_CONFIG_VAL, 128u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P2_U0_BASE), BS_UDB_1_3_0_CONFIG_VAL, 128u},\r
};\r
\r
uint8 CYDATA i;\r
\r
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);\r
\r
+ /* Perform normal device configuration. Order is not critical for these items. */\r
+ CYMEMZERO((void CYFAR *)(CYREG_PHUB_CFGMEM0_CFG0), 4u);\r
+ CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM1_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM1_VAL), 4u);\r
+ CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM2_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM2_VAL), 4u);\r
+ CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM3_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM3_VAL), 4u);\r
+\r
/* Enable digital routing */\r
CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);\r
CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);\r
/* Debug_Timer_Interrupt */\r
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set Debug_Timer_Interrupt__INTC_MASK, 0x01\r
-.set Debug_Timer_Interrupt__INTC_NUMBER, 0\r
+.set Debug_Timer_Interrupt__INTC_MASK, 0x02\r
+.set Debug_Timer_Interrupt__INTC_NUMBER, 1\r
.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7\r
-.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_RX_DMA_COMPLETE */\r
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01\r
+.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA_COMPLETE */\r
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x04\r
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 2\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
/* Debug_Timer_TimerHW */\r
.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0\r
.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1\r
.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1\r
.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0\r
\r
+/* SD_RX_DMA_COMPLETE */\r
+.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x08\r
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 3\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
+.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SD_TX_DMA_COMPLETE */\r
+.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x10\r
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 4\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
+.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
/* USBFS_bus_reset */\r
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
\r
/* SCSI_Out_Bits */\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
\r
/* USBFS_arb_int */\r
.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
/* SCSI_Out_Ctl */\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK\r
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB06_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB06_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB04_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB04_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1\r
\r
/* USBFS_dp_int */\r
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_In_DBx__DB7__SHIFT, 1\r
.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW\r
\r
+/* SCSI_RX_DMA */\r
+.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SCSI_RX_DMA__DRQ_NUMBER, 0\r
+.set SCSI_RX_DMA__NUMBEROF_TDS, 0\r
+.set SCSI_RX_DMA__PRIORITY, 2\r
+.set SCSI_RX_DMA__TERMIN_EN, 0\r
+.set SCSI_RX_DMA__TERMIN_SEL, 0\r
+.set SCSI_RX_DMA__TERMOUT0_EN, 1\r
+.set SCSI_RX_DMA__TERMOUT0_SEL, 0\r
+.set SCSI_RX_DMA__TERMOUT1_EN, 0\r
+.set SCSI_RX_DMA__TERMOUT1_SEL, 0\r
+\r
+/* SCSI_TX_DMA */\r
+.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SCSI_TX_DMA__DRQ_NUMBER, 1\r
+.set SCSI_TX_DMA__NUMBEROF_TDS, 0\r
+.set SCSI_TX_DMA__PRIORITY, 2\r
+.set SCSI_TX_DMA__TERMIN_EN, 0\r
+.set SCSI_TX_DMA__TERMIN_SEL, 0\r
+.set SCSI_TX_DMA__TERMOUT0_EN, 1\r
+.set SCSI_TX_DMA__TERMOUT0_SEL, 1\r
+.set SCSI_TX_DMA__TERMOUT1_EN, 0\r
+.set SCSI_TX_DMA__TERMOUT1_SEL, 0\r
+\r
/* SD_Data_Clk */\r
.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0\r
.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1\r
/* scsiTarget */\r
.set scsiTarget_StatusReg__0__MASK, 0x01\r
.set scsiTarget_StatusReg__0__POS, 0\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__2__POS, 2\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__3__POS, 3\r
-.set scsiTarget_StatusReg__MASK, 0x0F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB13_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB13_ST\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB12_MSK\r
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB12_ST\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB12_CTL\r
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB12_CTL\r
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB12_MSK\r
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB12_13_A0\r
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB12_13_A1\r
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB12_13_D0\r
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB12_13_D1\r
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB12_13_F0\r
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB12_13_F1\r
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB12_A0_A1\r
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB12_A0\r
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB12_A1\r
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB12_D0_D1\r
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB12_D0\r
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB12_D1\r
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB12_F0_F1\r
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB12_F0\r
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB12_F1\r
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_StatusReg__4__MASK, 0x10\r
+.set scsiTarget_StatusReg__4__POS, 4\r
+.set scsiTarget_StatusReg__MASK, 0x1F\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK\r
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL\r
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL\r
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK\r
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYR
projects / SCSI2SD-V6.git / commitdiff