Few bug fixes to wait for SD card to be finished
authorMichael McMaster <michael@codesrc.com>
Mon, 3 May 2021 04:25:56 +0000 (14:25 +1000)
committerMichael McMaster <michael@codesrc.com>
Mon, 3 May 2021 04:25:56 +0000 (14:25 +1000)
src/firmware/config.c
src/firmware/disk.c
src/firmware/fpga.c
src/firmware/scsiPhy.c

index e75be816c4983835776a2fc7ac7ebfef7cdae28d..5f25635af9b107420fd9cc6f0bac35eb446ff32b 100755 (executable)
@@ -36,7 +36,7 @@
 \r
 #include <string.h>\r
 \r
-static const uint16_t FIRMWARE_VERSION = 0x0641;\r
+static const uint16_t FIRMWARE_VERSION = 0x0642;\r
 \r
 // Optional static config\r
 extern uint8_t* __fixed_config;\r
index 1f849eca17c93349584e3918c5bce3823053264a..7c4c5bce2047ec47c3535449d95f096d20f011c7 100755 (executable)
@@ -635,7 +635,8 @@ void scsiDiskPoll()
                                (prep - i < buffers) &&\r
                                (prep < totalSDSectors) &&\r
                                ((totalSDSectors - prep) >= sdPerScsi) &&\r
-                               (likely(!useSlowDataCount) || scsiPhyComplete()))\r
+                               (likely(!useSlowDataCount) || scsiPhyComplete()) &&\r
+                               (HAL_SD_GetState(&hsd) != HAL_SD_STATE_BUSY)) // rx complete but IRQ not fired yet.\r
                        {\r
                                // Start an SD transfer if we have space.\r
                                uint32_t startBuffer = prep % buffers;\r
@@ -714,6 +715,11 @@ void scsiDiskPoll()
                }\r
                __enable_irq();\r
 \r
+               while (HAL_SD_GetState(&hsd) == HAL_SD_STATE_BUSY)\r
+               {\r
+                       // Wait while keeping BSY.\r
+               }\r
+\r
                if (scsiDev.phase == DATA_IN)\r
                {\r
                        scsiDev.phase = STATUS;\r
index 460d908887f62308291075d024d76f28e255d4d0..752488b22f4d314d58599033100c5ec9fac499f7 100755 (executable)
@@ -76,7 +76,7 @@ void s2s_fpgaInit()
 void s2s_fpgaReset()
 {
        HAL_GPIO_WritePin(FPGA_RST_GPIO_Port, FPGA_RST_Pin, GPIO_PIN_SET);
-       s2s_delay_clocks(4);
+       s2s_delay_clocks(12);
        HAL_GPIO_WritePin(FPGA_RST_GPIO_Port, FPGA_RST_Pin, GPIO_PIN_RESET);
 }
 
index b90fd6c63bb7b9266d41b19a4e2562110e186327..b7b55e027a5ab69640d9b0ba29ab308552628159 100755 (executable)
@@ -94,6 +94,11 @@ scsiSetDataCount(uint32_t count)
        *SCSI_DATA_CNT_MID = (count >> 8) & 0xff;\r
        *SCSI_DATA_CNT_LO = count & 0xff;\r
        *SCSI_DATA_CNT_SET = 1;\r
+\r
+#ifdef STM32F4xx\r
+       __NOP();\r
+       __NOP();\r
+#endif\r
 }\r
 \r
 int scsiFifoReady(void)\r
@@ -106,6 +111,8 @@ int scsiFifoReady(void)
        __NOP();\r
 #ifdef STM32F4xx\r
        __NOP();\r
+       __NOP();\r
+       __NOP();\r
 #endif\r
        return HAL_GPIO_ReadPin(GPIOE, FPGA_GPIO3_Pin) != 0;\r
 }\r