f2497a0b7d2668ec922d45a39ef590aa413e9609
[SCSI2SD.git] / software / SCSI2SD / SCSI2SD.cydsn / Generated_Source / PSoC5 / cyfitter_cfg.c
1 /*******************************************************************************\r
2 * FILENAME: cyfitter_cfg.c\r
3 * PSoC Creator 3.0 Component Pack 7\r
4 *\r
5 * Description:\r
6 * This file is automatically generated by PSoC Creator with device \r
7 * initialization code.  Except for the user defined sections in\r
8 * CyClockStartupError(), this file should not be modified.\r
9 *\r
10 ********************************************************************************\r
11 * Copyright 2013, Cypress Semiconductor Corporation.  All rights reserved.\r
12 * You may use this file only in accordance with the license, terms, conditions, \r
13 * disclaimers, and limitations in the end user license agreement accompanying \r
14 * the software package with which this file was provided.\r
15 ********************************************************************************/\r
16 \r
17 #include <string.h>\r
18 #include <cytypes.h>\r
19 #include <cydevice_trm.h>\r
20 #include <cyfitter.h>\r
21 #include <CyLib.h>\r
22 #include <cyfitter_cfg.h>\r
23 \r
24 #define CY_NEED_CYCLOCKSTARTUPERROR 1\r
25 \r
26 \r
27 #if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
28     #define CYPACKED \r
29     #define CYPACKED_ATTR __attribute__ ((packed))\r
30     #define CYALIGNED __attribute__ ((aligned))\r
31     #define CY_CFG_UNUSED __attribute__ ((unused))\r
32     #define CY_CFG_SECTION __attribute__ ((section(".psocinit")))\r
33     \r
34     #if defined(__ARMCC_VERSION)\r
35         #define CY_CFG_MEMORY_BARRIER() __memory_changed()\r
36     #else\r
37         #define CY_CFG_MEMORY_BARRIER() __sync_synchronize()\r
38     #endif\r
39     \r
40 #elif defined(__ICCARM__)\r
41     #include <intrinsics.h>\r
42 \r
43     #define CYPACKED __packed\r
44     #define CYPACKED_ATTR \r
45     #define CYALIGNED _Pragma("data_alignment=4")\r
46     #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177")\r
47     #define CY_CFG_SECTION _Pragma("location=\".psocinit\"")\r
48     \r
49     #define CY_CFG_MEMORY_BARRIER() __DMB()\r
50     \r
51 #else\r
52     #error Unsupported toolchain\r
53 #endif\r
54 \r
55 \r
56 CY_CFG_UNUSED\r
57 static void CYMEMZERO(void *s, size_t n);\r
58 CY_CFG_UNUSED\r
59 static void CYMEMZERO(void *s, size_t n)\r
60 {\r
61         (void)memset(s, 0, n);\r
62 }\r
63 CY_CFG_UNUSED\r
64 static void CYCONFIGCPY(void *dest, const void *src, size_t n);\r
65 CY_CFG_UNUSED\r
66 static void CYCONFIGCPY(void *dest, const void *src, size_t n)\r
67 {\r
68         (void)memcpy(dest, src, n);\r
69 }\r
70 CY_CFG_UNUSED\r
71 static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);\r
72 CY_CFG_UNUSED\r
73 static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)\r
74 {\r
75         (void)memcpy(dest, src, n);\r
76 }\r
77 \r
78 \r
79 \r
80 /* Clock startup error codes                                                   */\r
81 #define CYCLOCKSTART_NO_ERROR    0u\r
82 #define CYCLOCKSTART_XTAL_ERROR  1u\r
83 #define CYCLOCKSTART_32KHZ_ERROR 2u\r
84 #define CYCLOCKSTART_PLL_ERROR   3u\r
85 \r
86 #ifdef CY_NEED_CYCLOCKSTARTUPERROR\r
87 /*******************************************************************************\r
88 * Function Name: CyClockStartupError\r
89 ********************************************************************************\r
90 * Summary:\r
91 *  If an error is encountered during clock configuration (crystal startup error,\r
92 *  PLL lock error, etc.), the system will end up here.  Unless reimplemented by\r
93 *  the customer, this function will stop in an infinite loop.\r
94 *\r
95 * Parameters:\r
96 *   void\r
97 *\r
98 * Return:\r
99 *   void\r
100 *\r
101 *******************************************************************************/\r
102 CY_CFG_UNUSED\r
103 static void CyClockStartupError(uint8 errorCode);\r
104 CY_CFG_UNUSED\r
105 static void CyClockStartupError(uint8 errorCode)\r
106 {\r
107     /* To remove the compiler warning if errorCode not used.                */\r
108     errorCode = errorCode;\r
109 \r
110     /* `#START CyClockStartupError` */\r
111 \r
112     /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.),  */\r
113     /* we will end up here to allow the customer to implement something to  */\r
114     /* deal with the clock condition.                                       */\r
115 \r
116     /* `#END` */\r
117 \r
118     /* If nothing else, stop here since the clocks have not started         */\r
119     /* correctly.                                                           */\r
120     while(1) {}\r
121 }\r
122 #endif\r
123 \r
124 #define CY_CFG_BASE_ADDR_COUNT 37u\r
125 CYPACKED typedef struct\r
126 {\r
127         uint8 offset;\r
128         uint8 value;\r
129 } CYPACKED_ATTR cy_cfg_addrvalue_t;\r
130 \r
131 \r
132 \r
133 /*******************************************************************************\r
134 * Function Name: cfg_write_bytes32\r
135 ********************************************************************************\r
136 * Summary:\r
137 *  This function is used for setting up the chip configuration areas that\r
138 *  contain relatively sparse data.\r
139 *\r
140 * Parameters:\r
141 *   void\r
142 *\r
143 * Return:\r
144 *   void\r
145 *\r
146 *******************************************************************************/\r
147 static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]);\r
148 static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[])\r
149 {\r
150         /* For 32-bit little-endian architectures */\r
151         uint32 i, j = 0u;\r
152         for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++)\r
153         {\r
154                 uint32 baseAddr = addr_table[i];\r
155                 uint8 count = (uint8)baseAddr;\r
156                 baseAddr &= 0xFFFFFF00u;\r
157                 while (count != 0u)\r
158                 {\r
159                         CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value);\r
160                         j++;\r
161                         count--;\r
162                 }\r
163         }\r
164 }\r
165 \r
166 /*******************************************************************************\r
167 * Function Name: ClockSetup\r
168 ********************************************************************************\r
169 *\r
170 * Summary:\r
171 *  Performs the initialization of all of the clocks in the device based on the\r
172 *  settings in the Clock tab of the DWR.  This includes enabling the requested\r
173 *  clocks and setting the necessary dividers to produce the desired frequency. \r
174 *\r
175 * Parameters:\r
176 *  void\r
177 *\r
178 * Return:\r
179 *  void\r
180 *\r
181 *******************************************************************************/\r
182 static void ClockSetup(void);\r
183 static void ClockSetup(void)\r
184 {\r
185         uint32 timeout;\r
186         uint8 pllLock;\r
187 \r
188 \r
189         /* Configure Digital Clocks based on settings from Clock DWR */\r
190         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0000u);\r
191         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u);\r
192         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0000u);\r
193         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x58u);\r
194         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u);\r
195         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);\r
196         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0), 0x001Du);\r
197         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0 + 0x2u), 0x19u);\r
198 \r
199         /* Configure ILO based on settings from Clock DWR */\r
200         CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);\r
201 \r
202         /* Configure IMO based on settings from Clock DWR */\r
203         CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u);\r
204         CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB)));\r
205 \r
206         /* Configure PLL based on settings from Clock DWR */\r
207         CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0B19u);\r
208         CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);\r
209         /* Wait up to 250us for the PLL to lock */\r
210         pllLock = 0u;\r
211         for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--)\r
212         { \r
213                 pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0));\r
214                 CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */\r
215         }\r
216         /* If we ran out of time the PLL didn't lock so go to the error function */\r
217         if (timeout == 0u)\r
218         {\r
219                 CyClockStartupError(CYCLOCKSTART_PLL_ERROR);\r
220         }\r
221 \r
222         /* Configure Bus/Master Clock based on settings from Clock DWR */\r
223         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u);\r
224         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u);\r
225         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u);\r
226         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u);\r
227         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u);\r
228 \r
229         /* Configure USB Clock based on settings from Clock DWR */\r
230         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);\r
231         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);\r
232 \r
233         CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x0Fu)));\r
234 }\r
235 \r
236 \r
237 /* Analog API Functions */\r
238 \r
239 \r
240 /*******************************************************************************\r
241 * Function Name: AnalogSetDefault\r
242 ********************************************************************************\r
243 *\r
244 * Summary:\r
245 *  Sets up the analog portions of the chip to default values based on chip\r
246 *  configuration options from the project.\r
247 *\r
248 * Parameters:\r
249 *  void\r
250 *\r
251 * Return:\r
252 *  void\r
253 *\r
254 *******************************************************************************/\r
255 static void AnalogSetDefault(void);\r
256 static void AnalogSetDefault(void)\r
257 {\r
258         uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u));\r
259         CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u));\r
260         CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu));\r
261         CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);\r
262 }\r
263 \r
264 \r
265 /*******************************************************************************\r
266 * Function Name: SetAnalogRoutingPumps\r
267 ********************************************************************************\r
268 *\r
269 * Summary:\r
270 * Enables or disables the analog pumps feeding analog routing switches.\r
271 * Intended to be called at startup, based on the Vdda system configuration;\r
272 * may be called during operation when the user informs us that the Vdda voltage\r
273 * crossed the pump threshold.\r
274 *\r
275 * Parameters:\r
276 *  enabled - 1 to enable the pumps, 0 to disable the pumps\r
277 *\r
278 * Return:\r
279 *  void\r
280 *\r
281 *******************************************************************************/\r
282 void SetAnalogRoutingPumps(uint8 enabled)\r
283 {\r
284         uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0);\r
285         if (enabled != 0u)\r
286         {\r
287                 regValue |= 0x00u;\r
288         }\r
289         else\r
290         {\r
291                 regValue &= (uint8)~0x00u;\r
292         }\r
293         CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue);\r
294 }\r
295 \r
296 #define CY_AMUX_UNUSED CYREG_BOOST_SR\r
297 \r
298 \r
299 /*******************************************************************************\r
300 * Function Name: cyfitter_cfg\r
301 ********************************************************************************\r
302 * Summary:\r
303 *  This function is called by the start-up code for the selected device. It\r
304 *  performs all of the necessary device configuration based on the design\r
305 *  settings.  This includes settings from the Design Wide Resources (DWR) such\r
306 *  as Clocks and Pins as well as any component configuration that is necessary.\r
307 *\r
308 * Parameters:  \r
309 *   void\r
310 *\r
311 * Return:\r
312 *   void\r
313 *\r
314 *******************************************************************************/\r
315 \r
316 void cyfitter_cfg(void)\r
317 {\r
318         /* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */\r
319         static const uint8 CYCODE BS_IOPINS0_0_VAL[] = {\r
320                 0x00u, 0xFFu, 0xFFu, 0x00u, 0x17u, 0x00u, 0x00u, 0x00u};\r
321 \r
322         /* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */\r
323         static const uint8 CYCODE BS_IOPINS0_7_VAL[] = {\r
324                 0x08u, 0x00u, 0x30u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
325 \r
326         /* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */\r
327         static const uint8 CYCODE BS_IOPINS1_7_VAL[] = {\r
328                 0x00u, 0x00u, 0x00u, 0x00u, 0x10u};\r
329 \r
330         /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */\r
331         static const uint8 CYCODE BS_IOPINS0_8_VAL[] = {\r
332                 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u};\r
333 \r
334         /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */\r
335         static const uint8 CYCODE BS_IOPINS0_2_VAL[] = {\r
336                 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u};\r
337 \r
338         /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */\r
339         static const uint8 CYCODE BS_IOPINS0_3_VAL[] = {\r
340                 0x10u, 0x00u, 0x63u, 0x1Cu, 0x1Cu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u};\r
341 \r
342         /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */\r
343         static const uint8 CYCODE BS_IOPINS0_4_VAL[] = {\r
344                 0x00u, 0xFCu, 0xFCu, 0x00u, 0xF8u, 0x00u, 0x00u, 0x00u};\r
345 \r
346         /* IOPINS0_5 Address: CYREG_PRT5_DM0 Size (bytes): 8 */\r
347         static const uint8 CYCODE BS_IOPINS0_5_VAL[] = {\r
348                 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u};\r
349 \r
350         /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */\r
351         static const uint8 CYCODE BS_IOPINS0_6_VAL[] = {\r
352                 0xF0u, 0x0Fu, 0x0Fu, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x01u};\r
353 \r
354         /* PHUB_CFGMEM1 Address: CYREG_PHUB_CFGMEM1_CFG0 Size (bytes): 4 */\r
355         static const uint8 CYCODE BS_PHUB_CFGMEM1_VAL[] = {\r
356                 0x00u, 0x01u, 0x00u, 0x00u};\r
357 \r
358         /* PHUB_CFGMEM2 Address: CYREG_PHUB_CFGMEM2_CFG0 Size (bytes): 4 */\r
359         static const uint8 CYCODE BS_PHUB_CFGMEM2_VAL[] = {\r
360                 0x00u, 0x02u, 0x00u, 0x00u};\r
361 \r
362         /* PHUB_CFGMEM3 Address: CYREG_PHUB_CFGMEM3_CFG0 Size (bytes): 4 */\r
363         static const uint8 CYCODE BS_PHUB_CFGMEM3_VAL[] = {\r
364                 0x00u, 0x03u, 0x00u, 0x00u};\r
365 \r
366 #ifdef CYGlobalIntDisable\r
367         /* Disable interrupts by default. Let user enable if/when they want. */\r
368         CYGlobalIntDisable\r
369 #endif\r
370 \r
371 \r
372         /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */\r
373         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u));\r
374         /* Setup clocks based on selections from Clock DWR */\r
375         ClockSetup();\r
376         /* Set Flash Cycles based on newly configured 50.00MHz Bus Clock. */\r
377         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0xC1u : 0xC0u));\r
378         /* Enable/Disable Debug functionality based on settings from System DWR */\r
379         CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u));\r
380 \r
381         {\r
382                 static const uint32 CYCODE cy_cfg_addr_table[] = {\r
383                         0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
384                         0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
385                         0x4000520Au, /* Base address: 0x40005200 Count: 10 */\r
386                         0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
387                         0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
388                         0x40010052u, /* Base address: 0x40010000 Count: 82 */\r
389                         0x40010139u, /* Base address: 0x40010100 Count: 57 */\r
390                         0x40010241u, /* Base address: 0x40010200 Count: 65 */\r
391                         0x4001035Cu, /* Base address: 0x40010300 Count: 92 */\r
392                         0x40010417u, /* Base address: 0x40010400 Count: 23 */\r
393                         0x40010560u, /* Base address: 0x40010500 Count: 96 */\r
394                         0x4001065Du, /* Base address: 0x40010600 Count: 93 */\r
395                         0x40010754u, /* Base address: 0x40010700 Count: 84 */\r
396                         0x40010804u, /* Base address: 0x40010800 Count: 4 */\r
397                         0x4001090Eu, /* Base address: 0x40010900 Count: 14 */\r
398                         0x40010B12u, /* Base address: 0x40010B00 Count: 18 */\r
399                         0x40010C47u, /* Base address: 0x40010C00 Count: 71 */\r
400                         0x40010D45u, /* Base address: 0x40010D00 Count: 69 */\r
401                         0x40010F05u, /* Base address: 0x40010F00 Count: 5 */\r
402                         0x40011505u, /* Base address: 0x40011500 Count: 5 */\r
403                         0x4001164Cu, /* Base address: 0x40011600 Count: 76 */\r
404                         0x4001174Bu, /* Base address: 0x40011700 Count: 75 */\r
405                         0x4001190Au, /* Base address: 0x40011900 Count: 10 */\r
406                         0x40011B03u, /* Base address: 0x40011B00 Count: 3 */\r
407                         0x40014019u, /* Base address: 0x40014000 Count: 25 */\r
408                         0x40014117u, /* Base address: 0x40014100 Count: 23 */\r
409                         0x4001420Fu, /* Base address: 0x40014200 Count: 15 */\r
410                         0x4001430Du, /* Base address: 0x40014300 Count: 13 */\r
411                         0x4001440Du, /* Base address: 0x40014400 Count: 13 */\r
412                         0x40014516u, /* Base address: 0x40014500 Count: 22 */\r
413                         0x40014608u, /* Base address: 0x40014600 Count: 8 */\r
414                         0x40014705u, /* Base address: 0x40014700 Count: 5 */\r
415                         0x40014807u, /* Base address: 0x40014800 Count: 7 */\r
416                         0x4001490Au, /* Base address: 0x40014900 Count: 10 */\r
417                         0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
418                         0x40015005u, /* Base address: 0x40015000 Count: 5 */\r
419                         0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
420                 };\r
421 \r
422                 static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
423                         {0x36u, 0x02u},\r
424                         {0x7Eu, 0x02u},\r
425                         {0x01u, 0x20u},\r
426                         {0x0Au, 0x1Bu},\r
427                         {0x00u, 0x14u},\r
428                         {0x01u, 0x01u},\r
429                         {0x18u, 0x0Cu},\r
430                         {0x19u, 0x08u},\r
431                         {0x1Cu, 0x61u},\r
432                         {0x20u, 0x60u},\r
433                         {0x21u, 0xC0u},\r
434                         {0x30u, 0x06u},\r
435                         {0x31u, 0x0Cu},\r
436                         {0x7Cu, 0x40u},\r
437                         {0x23u, 0x02u},\r
438                         {0x86u, 0x0Fu},\r
439                         {0x00u, 0x03u},\r
440                         {0x01u, 0x09u},\r
441                         {0x02u, 0x0Cu},\r
442                         {0x03u, 0x24u},\r
443                         {0x04u, 0x09u},\r
444                         {0x06u, 0x06u},\r
445                         {0x07u, 0x09u},\r
446                         {0x08u, 0xFFu},\r
447                         {0x09u, 0x40u},\r
448                         {0x0Cu, 0x90u},\r
449                         {0x0Eu, 0x60u},\r
450                         {0x0Fu, 0x30u},\r
451                         {0x10u, 0xFFu},\r
452                         {0x11u, 0x09u},\r
453                         {0x13u, 0x12u},\r
454                         {0x14u, 0x05u},\r
455                         {0x15u, 0x40u},\r
456                         {0x16u, 0x0Au},\r
457                         {0x1Bu, 0x01u},\r
458                         {0x1Cu, 0x0Fu},\r
459                         {0x1Eu, 0xF0u},\r
460                         {0x1Fu, 0x06u},\r
461                         {0x20u, 0x50u},\r
462                         {0x22u, 0xA0u},\r
463                         {0x23u, 0x08u},\r
464                         {0x25u, 0x80u},\r
465                         {0x26u, 0xFFu},\r
466                         {0x29u, 0x40u},\r
467                         {0x2Cu, 0x30u},\r
468                         {0x2Du, 0x40u},\r
469                         {0x2Eu, 0xC0u},\r
470                         {0x31u, 0x38u},\r
471                         {0x32u, 0xFFu},\r
472                         {0x33u, 0x40u},\r
473                         {0x35u, 0x80u},\r
474                         {0x37u, 0x07u},\r
475                         {0x39u, 0x08u},\r
476                         {0x3Eu, 0x04u},\r
477                         {0x3Fu, 0x14u},\r
478                         {0x58u, 0x04u},\r
479                         {0x59u, 0x04u},\r
480                         {0x5Cu, 0x10u},\r
481                         {0x5Fu, 0x01u},\r
482                         {0x81u, 0x10u},\r
483                         {0x83u, 0x20u},\r
484                         {0x85u, 0x43u},\r
485                         {0x86u, 0xC1u},\r
486                         {0x87u, 0x04u},\r
487                         {0x89u, 0x45u},\r
488                         {0x8Au, 0x04u},\r
489                         {0x8Bu, 0x02u},\r
490                         {0x8Du, 0x08u},\r
491                         {0x8Eu, 0x02u},\r
492                         {0x90u, 0x24u},\r
493                         {0x91u, 0x41u},\r
494                         {0x92u, 0x90u},\r
495                         {0x93u, 0x06u},\r
496                         {0x95u, 0x04u},\r
497                         {0x96u, 0x24u},\r
498                         {0x97u, 0x03u},\r
499                         {0x9Au, 0x18u},\r
500                         {0x9Fu, 0x10u},\r
501                         {0xA0u, 0x01u},\r
502                         {0xA2u, 0x02u},\r
503                         {0xA6u, 0x20u},\r
504                         {0xA8u, 0x24u},\r
505                         {0xAAu, 0x48u},\r
506                         {0xABu, 0x20u},\r
507                         {0xB1u, 0x08u},\r
508                         {0xB2u, 0xE0u},\r
509                         {0xB3u, 0x07u},\r
510                         {0xB4u, 0x1Cu},\r
511                         {0xB5u, 0x30u},\r
512                         {0xB6u, 0x03u},\r
513                         {0xB7u, 0x40u},\r
514                         {0xBBu, 0x08u},\r
515                         {0xBEu, 0x40u},\r
516                         {0xBFu, 0x51u},\r
517                         {0xD8u, 0x04u},\r
518                         {0xD9u, 0x04u},\r
519                         {0xDCu, 0x01u},\r
520                         {0xDFu, 0x01u},\r
521                         {0x00u, 0x80u},\r
522                         {0x02u, 0xA0u},\r
523                         {0x03u, 0x08u},\r
524                         {0x05u, 0x14u},\r
525                         {0x07u, 0x01u},\r
526                         {0x08u, 0x40u},\r
527                         {0x09u, 0x05u},\r
528                         {0x0Au, 0x01u},\r
529                         {0x0Du, 0x25u},\r
530                         {0x0Fu, 0x08u},\r
531                         {0x11u, 0x84u},\r
532                         {0x12u, 0x04u},\r
533                         {0x13u, 0x22u},\r
534                         {0x14u, 0x40u},\r
535                         {0x15u, 0x20u},\r
536                         {0x16u, 0x20u},\r
537                         {0x18u, 0x10u},\r
538                         {0x1Du, 0x24u},\r
539                         {0x1Eu, 0x20u},\r
540                         {0x1Fu, 0x80u},\r
541                         {0x20u, 0x20u},\r
542                         {0x22u, 0xD0u},\r
543                         {0x23u, 0xC0u},\r
544                         {0x24u, 0x40u},\r
545                         {0x25u, 0x80u},\r
546                         {0x26u, 0x04u},\r
547                         {0x27u, 0x28u},\r
548                         {0x28u, 0x08u},\r
549                         {0x2Au, 0x02u},\r
550                         {0x2Bu, 0x22u},\r
551                         {0x2Cu, 0x04u},\r
552                         {0x31u, 0x01u},\r
553                         {0x32u, 0x44u},\r
554                         {0x33u, 0x10u},\r
555                         {0x36u, 0x06u},\r
556                         {0x37u, 0x80u},\r
557                         {0x38u, 0x10u},\r
558                         {0x39u, 0x0Au},\r
559                         {0x3Bu, 0x40u},\r
560                         {0x3Eu, 0x05u},\r
561                         {0x3Fu, 0x90u},\r
562                         {0x46u, 0x40u},\r
563                         {0x47u, 0x01u},\r
564                         {0x86u, 0x20u},\r
565                         {0x87u, 0x02u},\r
566                         {0x88u, 0x08u},\r
567                         {0x8Cu, 0x40u},\r
568                         {0x8Du, 0x01u},\r
569                         {0x8Fu, 0x08u},\r
570                         {0xC0u, 0xEFu},\r
571                         {0xC2u, 0x7Du},\r
572                         {0xC4u, 0x7Du},\r
573                         {0xCAu, 0x2Fu},\r
574                         {0xCCu, 0xDFu},\r
575                         {0xCEu, 0xFFu},\r
576                         {0xE2u, 0x08u},\r
577                         {0xE6u, 0x72u},\r
578                         {0x21u, 0x01u},\r
579                         {0x35u, 0x01u},\r
580                         {0x3Fu, 0x10u},\r
581                         {0x59u, 0x04u},\r
582                         {0x5Bu, 0x04u},\r
583                         {0x5Fu, 0x01u},\r
584                         {0x80u, 0x80u},\r
585                         {0x81u, 0x40u},\r
586                         {0x84u, 0x02u},\r
587                         {0x85u, 0x01u},\r
588                         {0x8Au, 0x1Fu},\r
589                         {0x8Bu, 0x20u},\r
590                         {0x8Cu, 0x5Bu},\r
591                         {0x8Du, 0x80u},\r
592                         {0x8Eu, 0x24u},\r
593                         {0x94u, 0x03u},\r
594                         {0x95u, 0x08u},\r
595                         {0x96u, 0x0Cu},\r
596                         {0x97u, 0x12u},\r
597                         {0x98u, 0x58u},\r
598                         {0x99u, 0x0Bu},\r
599                         {0x9Au, 0x24u},\r
600                         {0x9Bu, 0x24u},\r
601                         {0xA0u, 0x0Cu},\r
602                         {0xA1u, 0x34u},\r
603                         {0xA2u, 0x40u},\r
604                         {0xA3u, 0x0Bu},\r
605                         {0xA6u, 0x01u},\r
606                         {0xA8u, 0x40u},\r
607                         {0xAAu, 0x37u},\r
608                         {0xABu, 0x3Fu},\r
609                         {0xB0u, 0x1Fu},\r
610                         {0xB1u, 0x80u},\r
611                         {0xB2u, 0x20u},\r
612                         {0xB3u, 0x38u},\r
613                         {0xB4u, 0x80u},\r
614                         {0xB5u, 0x07u},\r
615                         {0xB6u, 0x40u},\r
616                         {0xB7u, 0x40u},\r
617                         {0xBEu, 0x54u},\r
618                         {0xBFu, 0x41u},\r
619                         {0xC0u, 0x64u},\r
620                         {0xC1u, 0x02u},\r
621                         {0xC2u, 0x30u},\r
622                         {0xC5u, 0xCDu},\r
623                         {0xC6u, 0x2Eu},\r
624                         {0xC7u, 0x0Fu},\r
625                         {0xC8u, 0x1Fu},\r
626                         {0xC9u, 0xFFu},\r
627                         {0xCAu, 0xFFu},\r
628                         {0xCBu, 0xFFu},\r
629                         {0xCFu, 0x2Cu},\r
630                         {0xD6u, 0x01u},\r
631                         {0xD8u, 0x04u},\r
632                         {0xD9u, 0x04u},\r
633                         {0xDAu, 0x04u},\r
634                         {0xDBu, 0x04u},\r
635                         {0xDCu, 0x11u},\r
636                         {0xDDu, 0x01u},\r
637                         {0xDFu, 0x01u},\r
638                         {0xE2u, 0xC0u},\r
639                         {0xE6u, 0x80u},\r
640                         {0xE8u, 0x40u},\r
641                         {0xE9u, 0x40u},\r
642                         {0xEEu, 0x08u},\r
643                         {0x00u, 0x02u},\r
644                         {0x01u, 0x08u},\r
645                         {0x03u, 0x0Au},\r
646                         {0x09u, 0x20u},\r
647                         {0x0Bu, 0x20u},\r
648                         {0x10u, 0x80u},\r
649                         {0x11u, 0x04u},\r
650                         {0x12u, 0x08u},\r
651                         {0x18u, 0x04u},\r
652                         {0x19u, 0x42u},\r
653                         {0x1Au, 0x10u},\r
654                         {0x1Bu, 0x02u},\r
655                         {0x21u, 0x34u},\r
656                         {0x22u, 0x09u},\r
657                         {0x23u, 0x05u},\r
658                         {0x27u, 0x04u},\r
659                         {0x29u, 0x02u},\r
660                         {0x2Bu, 0x08u},\r
661                         {0x2Cu, 0x08u},\r
662                         {0x2Du, 0x20u},\r
663                         {0x2Fu, 0x80u},\r
664                         {0x31u, 0x20u},\r
665                         {0x32u, 0x08u},\r
666                         {0x38u, 0x20u},\r
667                         {0x39u, 0x85u},\r
668                         {0x41u, 0x11u},\r
669                         {0x42u, 0x10u},\r
670                         {0x43u, 0x02u},\r
671                         {0x48u, 0x90u},\r
672                         {0x49u, 0x08u},\r
673                         {0x4Au, 0x08u},\r
674                         {0x50u, 0x58u},\r
675                         {0x5Au, 0xA2u},\r
676                         {0x5Bu, 0x04u},\r
677                         {0x60u, 0x44u},\r
678                         {0x61u, 0x08u},\r
679                         {0x63u, 0x01u},\r
680                         {0x69u, 0x10u},\r
681                         {0x6Au, 0x40u},\r
682                         {0x6Bu, 0x50u},\r
683                         {0x6Du, 0x64u},\r
684                         {0x71u, 0x10u},\r
685                         {0x72u, 0x22u},\r
686                         {0x73u, 0x40u},\r
687                         {0x81u, 0x40u},\r
688                         {0x82u, 0x40u},\r
689                         {0x87u, 0x80u},\r
690                         {0x89u, 0x05u},\r
691                         {0x8Au, 0x80u},\r
692                         {0x8Bu, 0x80u},\r
693                         {0x8Cu, 0x08u},\r
694                         {0x8Du, 0x40u},\r
695                         {0x8Fu, 0x08u},\r
696                         {0x90u, 0x40u},\r
697                         {0x92u, 0x20u},\r
698                         {0x93u, 0x20u},\r
699                         {0x94u, 0x80u},\r
700                         {0x95u, 0x2Eu},\r
701                         {0x96u, 0x0Du},\r
702                         {0x97u, 0x10u},\r
703                         {0x9Au, 0x44u},\r
704                         {0x9Bu, 0x80u},\r
705                         {0x9Cu, 0x08u},\r
706                         {0x9Du, 0x11u},\r
707                         {0x9Eu, 0x22u},\r
708                         {0x9Fu, 0x12u},\r
709                         {0xA1u, 0x80u},\r
710                         {0xA2u, 0x90u},\r
711                         {0xA3u, 0x04u},\r
712                         {0xA4u, 0x48u},\r
713                         {0xA5u, 0x44u},\r
714                         {0xA6u, 0x02u},\r
715                         {0xA7u, 0x20u},\r
716                         {0xABu, 0x40u},\r
717                         {0xACu, 0x10u},\r
718                         {0xAFu, 0x91u},\r
719                         {0xB0u, 0x04u},\r
720                         {0xB7u, 0x08u},\r
721                         {0xC0u, 0x0Fu},\r
722                         {0xC2u, 0x06u},\r
723                         {0xC4u, 0x0Eu},\r
724                         {0xCAu, 0x85u},\r
725                         {0xCCu, 0x06u},\r
726                         {0xCEu, 0x0Fu},\r
727                         {0xD0u, 0x07u},\r
728                         {0xD2u, 0x04u},\r
729                         {0xD6u, 0x0Fu},\r
730                         {0xD8u, 0x0Fu},\r
731                         {0xE2u, 0x20u},\r
732                         {0xE6u, 0x09u},\r
733                         {0xEAu, 0x06u},\r
734                         {0xEEu, 0x02u},\r
735                         {0x85u, 0x02u},\r
736                         {0x87u, 0x05u},\r
737                         {0x8Fu, 0x02u},\r
738                         {0x97u, 0x03u},\r
739                         {0x9Au, 0x01u},\r
740                         {0x9Fu, 0x0Cu},\r
741                         {0xA1u, 0x02u},\r
742                         {0xA2u, 0x04u},\r
743                         {0xA3u, 0x08u},\r
744                         {0xA4u, 0x05u},\r
745                         {0xA6u, 0x0Au},\r
746                         {0xAAu, 0x02u},\r
747                         {0xAEu, 0x08u},\r
748                         {0xB1u, 0x0Eu},\r
749                         {0xB4u, 0x0Cu},\r
750                         {0xB5u, 0x01u},\r
751                         {0xB6u, 0x03u},\r
752                         {0xBEu, 0x50u},\r
753                         {0xBFu, 0x10u},\r
754                         {0xD8u, 0x04u},\r
755                         {0xD9u, 0x04u},\r
756                         {0xDCu, 0x10u},\r
757                         {0xDFu, 0x01u},\r
758                         {0x01u, 0x41u},\r
759                         {0x03u, 0x18u},\r
760                         {0x04u, 0x80u},\r
761                         {0x05u, 0x80u},\r
762                         {0x08u, 0x48u},\r
763                         {0x0Au, 0x86u},\r
764                         {0x0Du, 0x80u},\r
765                         {0x0Fu, 0x0Au},\r
766                         {0x10u, 0x80u},\r
767                         {0x12u, 0x02u},\r
768                         {0x13u, 0x10u},\r
769                         {0x14u, 0x01u},\r
770                         {0x15u, 0x02u},\r
771                         {0x17u, 0x28u},\r
772                         {0x1Au, 0x82u},\r
773                         {0x1Bu, 0x10u},\r
774                         {0x1Fu, 0x90u},\r
775                         {0x20u, 0x40u},\r
776                         {0x22u, 0x10u},\r
777                         {0x27u, 0x84u},\r
778                         {0x29u, 0x02u},\r
779                         {0x2Du, 0x02u},\r
780                         {0x32u, 0x18u},\r
781                         {0x33u, 0x40u},\r
782                         {0x36u, 0x08u},\r
783                         {0x37u, 0x80u},\r
784                         {0x38u, 0x40u},\r
785                         {0x39u, 0x10u},\r
786                         {0x3Bu, 0x04u},\r
787                         {0x3Fu, 0x44u},\r
788                         {0x40u, 0x20u},\r
789                         {0x42u, 0x04u},\r
790                         {0x43u, 0x02u},\r
791                         {0x49u, 0x04u},\r
792                         {0x4Au, 0x02u},\r
793                         {0x4Bu, 0x11u},\r
794                         {0x50u, 0x08u},\r
795                         {0x51u, 0x60u},\r
796                         {0x53u, 0x01u},\r
797                         {0x58u, 0x04u},\r
798                         {0x59u, 0xA0u},\r
799                         {0x5Au, 0x01u},\r
800                         {0x61u, 0x40u},\r
801                         {0x64u, 0x02u},\r
802                         {0x67u, 0x02u},\r
803                         {0x79u, 0x02u},\r
804                         {0x7Au, 0x80u},\r
805                         {0x7Du, 0x08u},\r
806                         {0x7Eu, 0x10u},\r
807                         {0x80u, 0x08u},\r
808                         {0x83u, 0x05u},\r
809                         {0x85u, 0x40u},\r
810                         {0x88u, 0x20u},\r
811                         {0x8Bu, 0x10u},\r
812                         {0x8Fu, 0x80u},\r
813                         {0x90u, 0x80u},\r
814                         {0x91u, 0x14u},\r
815                         {0x92u, 0x40u},\r
816                         {0x93u, 0x44u},\r
817                         {0x96u, 0x0Cu},\r
818                         {0x97u, 0x10u},\r
819                         {0x98u, 0x04u},\r
820                         {0x99u, 0x62u},\r
821                         {0x9Au, 0x44u},\r
822                         {0x9Bu, 0x68u},\r
823                         {0xA0u, 0x10u},\r
824                         {0xA1u, 0x80u},\r
825                         {0xA2u, 0x98u},\r
826                         {0xA3u, 0x04u},\r
827                         {0xA4u, 0x40u},\r
828                         {0xA5u, 0x04u},\r
829                         {0xA6u, 0x02u},\r
830                         {0xA7u, 0x40u},\r
831                         {0xA9u, 0x29u},\r
832                         {0xABu, 0x20u},\r
833                         {0xACu, 0x84u},\r
834                         {0xADu, 0x40u},\r
835                         {0xB0u, 0x01u},\r
836                         {0xB2u, 0x01u},\r
837                         {0xB3u, 0x28u},\r
838                         {0xB5u, 0x10u},\r
839                         {0xB7u, 0x42u},\r
840                         {0xC0u, 0x0Fu},\r
841                         {0xC2u, 0x4Fu},\r
842                         {0xC4u, 0xFBu},\r
843                         {0xCAu, 0x81u},\r
844                         {0xCCu, 0x5Eu},\r
845                         {0xCEu, 0x5Eu},\r
846                         {0xD0u, 0x07u},\r
847                         {0xD2u, 0x0Cu},\r
848                         {0xD6u, 0x0Fu},\r
849                         {0xD8u, 0x08u},\r
850                         {0xE0u, 0x80u},\r
851                         {0xE2u, 0x40u},\r
852                         {0xEAu, 0x03u},\r
853                         {0xEEu, 0x54u},\r
854                         {0x00u, 0x01u},\r
855                         {0x03u, 0x9Fu},\r
856                         {0x04u, 0x01u},\r
857                         {0x07u, 0xFFu},\r
858                         {0x08u, 0x04u},\r
859                         {0x09u, 0x7Fu},\r
860                         {0x0Bu, 0x80u},\r
861                         {0x0Cu, 0x01u},\r
862                         {0x0Du, 0x90u},\r
863                         {0x0Fu, 0x40u},\r
864                         {0x11u, 0x1Fu},\r
865                         {0x12u, 0x40u},\r
866                         {0x13u, 0x20u},\r
867                         {0x14u, 0xA2u},\r
868                         {0x15u, 0x80u},\r
869                         {0x16u, 0x08u},\r
870                         {0x18u, 0x08u},\r
871                         {0x1Au, 0x61u},\r
872                         {0x1Bu, 0x60u},\r
873                         {0x1Cu, 0x01u},\r
874                         {0x1Du, 0xC0u},\r
875                         {0x1Fu, 0x02u},\r
876                         {0x20u, 0x07u},\r
877                         {0x21u, 0xC0u},\r
878                         {0x22u, 0xD8u},\r
879                         {0x23u, 0x01u},\r
880                         {0x25u, 0xC0u},\r
881                         {0x27u, 0x04u},\r
882                         {0x28u, 0x01u},\r
883                         {0x29u, 0xC0u},\r
884                         {0x2Bu, 0x08u},\r
885                         {0x2Cu, 0x10u},\r
886                         {0x30u, 0xE0u},\r
887                         {0x36u, 0x3Fu},\r
888                         {0x37u, 0xFFu},\r
889                         {0x38u, 0x80u},\r
890                         {0x3Eu, 0x40u},\r
891                         {0x3Fu, 0x40u},\r
892                         {0x58u, 0x04u},\r
893                         {0x59u, 0x04u},\r
894                         {0x5Fu, 0x01u},\r
895                         {0x80u, 0x56u},\r
896                         {0x81u, 0x64u},\r
897                         {0x84u, 0x52u},\r
898                         {0x85u, 0x83u},\r
899                         {0x86u, 0x04u},\r
900                         {0x87u, 0x70u},\r
901                         {0x88u, 0x50u},\r
902                         {0x8Au, 0x06u},\r
903                         {0x8Bu, 0xF5u},\r
904                         {0x8Cu, 0x17u},\r
905                         {0x8Du, 0x64u},\r
906                         {0x8Eu, 0x28u},\r
907                         {0x91u, 0x07u},\r
908                         {0x93u, 0x90u},\r
909                         {0x94u, 0x31u},\r
910                         {0x95u, 0x40u},\r
911                         {0x96u, 0x0Eu},\r
912                         {0x97u, 0x02u},\r
913                         {0x98u, 0x29u},\r
914                         {0x99u, 0x24u},\r
915                         {0x9Au, 0x16u},\r
916                         {0x9Bu, 0x40u},\r
917                         {0x9Du, 0x08u},\r
918                         {0xA0u, 0x56u},\r
919                         {0xA1u, 0x64u},\r
920                         {0xA4u, 0x22u},\r
921                         {0xA5u, 0x24u},\r
922                         {0xA6u, 0x10u},\r
923                         {0xA8u, 0x04u},\r
924                         {0xABu, 0x64u},\r
925                         {0xACu, 0x06u},\r
926                         {0xADu, 0x08u},\r
927                         {0xAEu, 0x50u},\r
928                         {0xB0u, 0x40u},\r
929                         {0xB1u, 0x71u},\r
930                         {0xB2u, 0x30u},\r
931                         {0xB3u, 0x07u},\r
932                         {0xB4u, 0x0Fu},\r
933                         {0xB5u, 0x08u},\r
934                         {0xB7u, 0x80u},\r
935                         {0xB8u, 0x20u},\r
936                         {0xB9u, 0x20u},\r
937                         {0xBAu, 0x08u},\r
938                         {0xBBu, 0x0Cu},\r
939                         {0xBEu, 0x01u},\r
940                         {0xBFu, 0x40u},\r
941                         {0xD4u, 0x40u},\r
942                         {0xD6u, 0x04u},\r
943                         {0xD8u, 0x04u},\r
944                         {0xD9u, 0x04u},\r
945                         {0xDBu, 0x04u},\r
946                         {0xDFu, 0x01u},\r
947                         {0x01u, 0x01u},\r
948                         {0x02u, 0x02u},\r
949                         {0x03u, 0x18u},\r
950                         {0x05u, 0x08u},\r
951                         {0x07u, 0x49u},\r
952                         {0x0Au, 0x04u},\r
953                         {0x0Bu, 0x10u},\r
954                         {0x0Cu, 0x80u},\r
955                         {0x0Eu, 0x84u},\r
956                         {0x0Fu, 0x10u},\r
957                         {0x10u, 0x98u},\r
958                         {0x11u, 0x40u},\r
959                         {0x15u, 0x82u},\r
960                         {0x17u, 0x10u},\r
961                         {0x18u, 0x08u},\r
962                         {0x19u, 0x09u},\r
963                         {0x1Au, 0x04u},\r
964                         {0x1Bu, 0x02u},\r
965                         {0x1Du, 0x40u},\r
966                         {0x1Eu, 0x80u},\r
967                         {0x21u, 0x01u},\r
968                         {0x22u, 0x62u},\r
969                         {0x23u, 0x18u},\r
970                         {0x25u, 0x80u},\r
971                         {0x28u, 0x10u},\r
972                         {0x29u, 0x48u},\r
973                         {0x2Bu, 0x88u},\r
974                         {0x2Cu, 0xA0u},\r
975                         {0x2Fu, 0x08u},\r
976                         {0x30u, 0x28u},\r
977                         {0x31u, 0x80u},\r
978                         {0x32u, 0x02u},\r
979                         {0x35u, 0x08u},\r
980                         {0x36u, 0x22u},\r
981                         {0x37u, 0x40u},\r
982                         {0x38u, 0x08u},\r
983                         {0x39u, 0x40u},\r
984                         {0x3Au, 0x02u},\r
985                         {0x3Bu, 0x10u},\r
986                         {0x3Du, 0x40u},\r
987                         {0x3Eu, 0x04u},\r
988                         {0x3Fu, 0x11u},\r
989                         {0x48u, 0x08u},\r
990                         {0x49u, 0x20u},\r
991                         {0x60u, 0x02u},\r
992                         {0x61u, 0x20u},\r
993                         {0x63u, 0xA0u},\r
994                         {0x86u, 0x40u},\r
995                         {0x88u, 0x01u},\r
996                         {0x91u, 0x84u},\r
997                         {0x92u, 0x60u},\r
998                         {0x93u, 0x05u},\r
999                         {0x95u, 0x41u},\r
1000                         {0x96u, 0x0Cu},\r
1001                         {0x97u, 0x10u},\r
1002                         {0x98u, 0x42u},\r
1003                         {0x99u, 0x06u},\r
1004                         {0x9Au, 0xC4u},\r
1005                         {0x9Bu, 0xA0u},\r
1006                         {0x9Cu, 0x01u},\r
1007                         {0x9Fu, 0x10u},\r
1008                         {0xA0u, 0x08u},\r
1009                         {0xA1u, 0x20u},\r
1010                         {0xA2u, 0x98u},\r
1011                         {0xA3u, 0x15u},\r
1012                         {0xA4u, 0x80u},\r
1013                         {0xA5u, 0x40u},\r
1014                         {0xA6u, 0x02u},\r
1015                         {0xA7u, 0x4Au},\r
1016                         {0xAAu, 0x10u},\r
1017                         {0xACu, 0x50u},\r
1018                         {0xAEu, 0x81u},\r
1019                         {0xB4u, 0x40u},\r
1020                         {0xC0u, 0xFFu},\r
1021                         {0xC2u, 0xF6u},\r
1022                         {0xC4u, 0xDFu},\r
1023                         {0xCAu, 0xEFu},\r
1024                         {0xCCu, 0xFFu},\r
1025                         {0xCEu, 0xFFu},\r
1026                         {0xD8u, 0x0Fu},\r
1027                         {0xE2u, 0x09u},\r
1028                         {0xE6u, 0x08u},\r
1029                         {0xEAu, 0x02u},\r
1030                         {0xECu, 0x04u},\r
1031                         {0x38u, 0x80u},\r
1032                         {0x3Eu, 0x40u},\r
1033                         {0x58u, 0x04u},\r
1034                         {0x5Fu, 0x01u},\r
1035                         {0x1Fu, 0x80u},\r
1036                         {0x8Au, 0x04u},\r
1037                         {0x92u, 0x0Cu},\r
1038                         {0x97u, 0x01u},\r
1039                         {0x9Bu, 0x80u},\r
1040                         {0x9Cu, 0x02u},\r
1041                         {0x9Du, 0x20u},\r
1042                         {0xA3u, 0x08u},\r
1043                         {0xAAu, 0x04u},\r
1044                         {0xADu, 0x40u},\r
1045                         {0xB5u, 0x08u},\r
1046                         {0xE2u, 0x09u},\r
1047                         {0xE6u, 0x28u},\r
1048                         {0xE8u, 0x40u},\r
1049                         {0x92u, 0x0Cu},\r
1050                         {0x97u, 0x01u},\r
1051                         {0x9Bu, 0x80u},\r
1052                         {0x9Cu, 0x02u},\r
1053                         {0x9Du, 0x28u},\r
1054                         {0xA1u, 0x40u},\r
1055                         {0xA3u, 0x08u},\r
1056                         {0xA6u, 0x04u},\r
1057                         {0xA8u, 0x40u},\r
1058                         {0xA9u, 0x04u},\r
1059                         {0xAEu, 0x04u},\r
1060                         {0xB0u, 0x20u},\r
1061                         {0xB1u, 0x01u},\r
1062                         {0xB6u, 0x08u},\r
1063                         {0xB7u, 0x08u},\r
1064                         {0xE0u, 0x20u},\r
1065                         {0xEAu, 0x94u},\r
1066                         {0xEEu, 0xA4u},\r
1067                         {0x01u, 0x0Fu},\r
1068                         {0x03u, 0xF0u},\r
1069                         {0x04u, 0x50u},\r
1070                         {0x05u, 0x30u},\r
1071                         {0x06u, 0xA0u},\r
1072                         {0x07u, 0xC0u},\r
1073                         {0x08u, 0x06u},\r
1074                         {0x09u, 0x50u},\r
1075                         {0x0Au, 0x09u},\r
1076                         {0x0Bu, 0xA0u},\r
1077                         {0x0Cu, 0x03u},\r
1078                         {0x0Du, 0x60u},\r
1079                         {0x0Eu, 0x0Cu},\r
1080                         {0x0Fu, 0x90u},\r
1081                         {0x11u, 0xFFu},\r
1082                         {0x12u, 0xFFu},\r
1083                         {0x14u, 0xFFu},\r
1084                         {0x15u, 0x05u},\r
1085                         {0x17u, 0x0Au},\r
1086                         {0x18u, 0x05u},\r
1087                         {0x19u, 0x06u},\r
1088                         {0x1Au, 0x0Au},\r
1089                         {0x1Bu, 0x09u},\r
1090                         {0x1Cu, 0x0Fu},\r
1091                         {0x1Eu, 0xF0u},\r
1092                         {0x1Fu, 0xFFu},\r
1093                         {0x21u, 0x03u},\r
1094                         {0x22u, 0xFFu},\r
1095                         {0x23u, 0x0Cu},\r
1096                         {0x24u, 0x30u},\r
1097                         {0x26u, 0xC0u},\r
1098                         {0x27u, 0xFFu},\r
1099                         {0x2Cu, 0x60u},\r
1100                         {0x2Eu, 0x90u},\r
1101                         {0x35u, 0xFFu},\r
1102                         {0x36u, 0xFFu},\r
1103                         {0x3Eu, 0x40u},\r
1104                         {0x3Fu, 0x10u},\r
1105                         {0x58u, 0x04u},\r
1106                         {0x59u, 0x04u},\r
1107                         {0x5Bu, 0x04u},\r
1108                         {0x5Fu, 0x01u},\r
1109                         {0x84u, 0x10u},\r
1110                         {0x86u, 0x09u},\r
1111                         {0x87u, 0x10u},\r
1112                         {0x8Bu, 0x08u},\r
1113                         {0x8Du, 0x0Au},\r
1114                         {0x8Fu, 0x14u},\r
1115                         {0x90u, 0x08u},\r
1116                         {0x92u, 0x10u},\r
1117                         {0x93u, 0x04u},\r
1118                         {0x94u, 0x04u},\r
1119                         {0x95u, 0x01u},\r
1120                         {0x9Cu, 0x19u},\r
1121                         {0x9Eu, 0x62u},\r
1122                         {0xA0u, 0x40u},\r
1123                         {0xA2u, 0x22u},\r
1124                         {0xABu, 0x02u},\r
1125                         {0xACu, 0x20u},\r
1126                         {0xAEu, 0x40u},\r
1127                         {0xB0u, 0x04u},\r
1128                         {0xB1u, 0x06u},\r
1129                         {0xB2u, 0x03u},\r
1130                         {0xB3u, 0x18u},\r
1131                         {0xB4u, 0x78u},\r
1132                         {0xB5u, 0x01u},\r
1133                         {0xBEu, 0x15u},\r
1134                         {0xBFu, 0x15u},\r
1135                         {0xD8u, 0x04u},\r
1136                         {0xD9u, 0x04u},\r
1137                         {0xDFu, 0x01u},\r
1138                         {0x01u, 0x08u},\r
1139                         {0x04u, 0x08u},\r
1140                         {0x05u, 0x20u},\r
1141                         {0x06u, 0x02u},\r
1142                         {0x09u, 0x06u},\r
1143                         {0x0Bu, 0x01u},\r
1144                         {0x0Cu, 0x01u},\r
1145                         {0x0Du, 0x50u},\r
1146                         {0x0Eu, 0x08u},\r
1147                         {0x0Fu, 0x21u},\r
1148                         {0x11u, 0x02u},\r
1149                         {0x12u, 0x01u},\r
1150                         {0x14u, 0x80u},\r
1151                         {0x15u, 0x44u},\r
1152                         {0x18u, 0xA0u},\r
1153                         {0x1Au, 0x08u},\r
1154                         {0x1Bu, 0x30u},\r
1155                         {0x1Fu, 0x80u},\r
1156                         {0x22u, 0x2Au},\r
1157                         {0x27u, 0x08u},\r
1158                         {0x29u, 0x20u},\r
1159                         {0x2Eu, 0x02u},\r
1160                         {0x2Fu, 0x20u},\r
1161                         {0x31u, 0x08u},\r
1162                         {0x33u, 0x02u},\r
1163                         {0x34u, 0x83u},\r
1164                         {0x35u, 0x20u},\r
1165                         {0x36u, 0x04u},\r
1166                         {0x38u, 0x08u},\r
1167                         {0x39u, 0xA0u},\r
1168                         {0x3Du, 0x91u},\r
1169                         {0x3Eu, 0x04u},\r
1170                         {0x3Fu, 0x01u},\r
1171                         {0x6Cu, 0x04u},\r
1172                         {0x6Du, 0xD6u},\r
1173                         {0x6Eu, 0x04u},\r
1174                         {0x6Fu, 0x0Au},\r
1175                         {0x74u, 0x20u},\r
1176                         {0x75u, 0x80u},\r
1177                         {0x76u, 0x11u},\r
1178                         {0x77u, 0x80u},\r
1179                         {0x82u, 0x20u},\r
1180                         {0x86u, 0x02u},\r
1181                         {0x88u, 0x80u},\r
1182                         {0x89u, 0x02u},\r
1183                         {0x8Au, 0x02u},\r
1184                         {0x8Cu, 0x10u},\r
1185                         {0x8Fu, 0x80u},\r
1186                         {0x9Cu, 0x02u},\r
1187                         {0x9Du, 0xA0u},\r
1188                         {0x9Eu, 0x10u},\r
1189                         {0x9Fu, 0x08u},\r
1190                         {0xA1u, 0x08u},\r
1191                         {0xA7u, 0x10u},\r
1192                         {0xAEu, 0x10u},\r
1193                         {0xB1u, 0x80u},\r
1194                         {0xB7u, 0x10u},\r
1195                         {0xC0u, 0xE4u},\r
1196                         {0xC2u, 0xFDu},\r
1197                         {0xC4u, 0xB9u},\r
1198                         {0xCAu, 0xC4u},\r
1199                         {0xCCu, 0xF3u},\r
1200                         {0xCEu, 0xFEu},\r
1201                         {0xE0u, 0xA2u},\r
1202                         {0xE2u, 0x50u},\r
1203                         {0xE4u, 0x20u},\r
1204                         {0xE6u, 0x98u},\r
1205                         {0xEAu, 0x14u},\r
1206                         {0xEEu, 0x82u},\r
1207                         {0x85u, 0x20u},\r
1208                         {0x87u, 0x08u},\r
1209                         {0x8Cu, 0x02u},\r
1210                         {0x8Du, 0x08u},\r
1211                         {0xE2u, 0x10u},\r
1212                         {0xAFu, 0x10u},\r
1213                         {0xB2u, 0x20u},\r
1214                         {0xB4u, 0x40u},\r
1215                         {0xEAu, 0x40u},\r
1216                         {0xECu, 0x02u},\r
1217                         {0x00u, 0x03u},\r
1218                         {0x02u, 0x0Cu},\r
1219                         {0x04u, 0x60u},\r
1220                         {0x05u, 0x01u},\r
1221                         {0x06u, 0x90u},\r
1222                         {0x07u, 0x02u},\r
1223                         {0x0Bu, 0x10u},\r
1224                         {0x0Cu, 0x0Fu},\r
1225                         {0x0Eu, 0xF0u},\r
1226                         {0x11u, 0x08u},\r
1227                         {0x13u, 0x10u},\r
1228                         {0x14u, 0x05u},\r
1229                         {0x16u, 0x0Au},\r
1230                         {0x17u, 0x01u},\r
1231                         {0x18u, 0x06u},\r
1232                         {0x1Au, 0x09u},\r
1233                         {0x1Bu, 0x06u},\r
1234                         {0x1Fu, 0x08u},\r
1235                         {0x20u, 0x50u},\r
1236                         {0x21u, 0x01u},\r
1237                         {0x22u, 0xA0u},\r
1238                         {0x23u, 0x04u},\r
1239                         {0x24u, 0x30u},\r
1240                         {0x26u, 0xC0u},\r
1241                         {0x2Fu, 0x01u},\r
1242                         {0x34u, 0xFFu},\r
1243                         {0x35u, 0x07u},\r
1244                         {0x37u, 0x18u},\r
1245                         {0x3Eu, 0x10u},\r
1246                         {0x3Fu, 0x40u},\r
1247                         {0x56u, 0x02u},\r
1248                         {0x57u, 0x28u},\r
1249                         {0x58u, 0x04u},\r
1250                         {0x59u, 0x04u},\r
1251                         {0x5Bu, 0x04u},\r
1252                         {0x5Cu, 0x10u},\r
1253                         {0x5Fu, 0x01u},\r
1254                         {0x86u, 0xECu},\r
1255                         {0x87u, 0xFFu},\r
1256                         {0x8Bu, 0xFFu},\r
1257                         {0x8Du, 0x0Fu},\r
1258                         {0x8Eu, 0x01u},\r
1259                         {0x8Fu, 0xF0u},\r
1260                         {0x91u, 0x30u},\r
1261                         {0x93u, 0xC0u},\r
1262                         {0x98u, 0x04u},\r
1263                         {0x99u, 0x05u},\r
1264                         {0x9Au, 0x43u},\r
1265                         {0x9Bu, 0x0Au},\r
1266                         {0x9Du, 0x03u},\r
1267                         {0x9Eu, 0x12u},\r
1268                         {0x9Fu, 0x0Cu},\r
1269                         {0xA0u, 0xE0u},\r
1270                         {0xA1u, 0x50u},\r
1271                         {0xA3u, 0xA0u},\r
1272                         {0xA7u, 0xFFu},\r
1273                         {0xA8u, 0x88u},\r
1274                         {0xA9u, 0x09u},\r
1275                         {0xAAu, 0x03u},\r
1276                         {0xABu, 0x06u},\r
1277                         {0xACu, 0x21u},\r
1278                         {0xADu, 0x90u},\r
1279                         {0xAEu, 0x02u},\r
1280                         {0xAFu, 0x60u},\r
1281                         {0xB0u, 0xE0u},\r
1282                         {0xB3u, 0xFFu},\r
1283                         {0xB4u, 0x0Fu},\r
1284                         {0xB6u, 0x10u},\r
1285                         {0xBEu, 0x01u},\r
1286                         {0xBFu, 0x04u},\r
1287                         {0xD4u, 0x09u},\r
1288                         {0xD6u, 0x04u},\r
1289                         {0xD8u, 0x04u},\r
1290                         {0xD9u, 0x04u},\r
1291                         {0xDBu, 0x04u},\r
1292                         {0xDFu, 0x01u},\r
1293                         {0x00u, 0x04u},\r
1294                         {0x01u, 0x80u},\r
1295                         {0x07u, 0xA2u},\r
1296                         {0x0Au, 0x04u},\r
1297                         {0x0Bu, 0x01u},\r
1298                         {0x0Eu, 0x20u},\r
1299                         {0x0Fu, 0x08u},\r
1300                         {0x10u, 0x40u},\r
1301                         {0x12u, 0x02u},\r
1302                         {0x13u, 0x10u},\r
1303                         {0x16u, 0x60u},\r
1304                         {0x18u, 0x44u},\r
1305                         {0x19u, 0x80u},\r
1306                         {0x1Fu, 0x10u},\r
1307                         {0x22u, 0x04u},\r
1308                         {0x25u, 0x40u},\r
1309                         {0x26u, 0x20u},\r
1310                         {0x28u, 0xA0u},\r
1311                         {0x29u, 0x10u},\r
1312                         {0x2Au, 0x80u},\r
1313                         {0x2Du, 0x02u},\r
1314                         {0x2Eu, 0x40u},\r
1315                         {0x30u, 0x01u},\r
1316                         {0x32u, 0x90u},\r
1317                         {0x35u, 0x10u},\r
1318                         {0x36u, 0x28u},\r
1319                         {0x37u, 0x82u},\r
1320                         {0x39u, 0x84u},\r
1321                         {0x3Bu, 0x20u},\r
1322                         {0x3Du, 0x20u},\r
1323                         {0x3Eu, 0x20u},\r
1324                         {0x3Fu, 0x04u},\r
1325                         {0x59u, 0x25u},\r
1326                         {0x5Au, 0x80u},\r
1327                         {0x63u, 0x82u},\r
1328                         {0x66u, 0x04u},\r
1329                         {0x69u, 0x80u},\r
1330                         {0x6Bu, 0x02u},\r
1331                         {0x6Cu, 0x20u},\r
1332                         {0x6Du, 0x41u},\r
1333                         {0x6Fu, 0xD9u},\r
1334                         {0x74u, 0x80u},\r
1335                         {0x76u, 0x02u},\r
1336                         {0x81u, 0x40u},\r
1337                         {0x8Fu, 0x40u},\r
1338                         {0x91u, 0x04u},\r
1339                         {0x92u, 0xE4u},\r
1340                         {0x93u, 0x15u},\r
1341                         {0x95u, 0x41u},\r
1342                         {0x96u, 0x08u},\r
1343                         {0x98u, 0xE1u},\r
1344                         {0x99u, 0x27u},\r
1345                         {0x9Au, 0xC4u},\r
1346                         {0x9Bu, 0xA0u},\r
1347                         {0x9Eu, 0x02u},\r
1348                         {0x9Fu, 0x51u},\r
1349                         {0xA1u, 0x10u},\r
1350                         {0xA2u, 0x9Au},\r
1351                         {0xA3u, 0x05u},\r
1352                         {0xA4u, 0xA0u},\r
1353                         {0xA5u, 0x40u},\r
1354                         {0xA7u, 0x88u},\r
1355                         {0xB0u, 0xA0u},\r
1356                         {0xB5u, 0x10u},\r
1357                         {0xC0u, 0xB5u},\r
1358                         {0xC2u, 0x63u},\r
1359                         {0xC4u, 0x3Bu},\r
1360                         {0xCAu, 0x9Fu},\r
1361                         {0xCCu, 0xFDu},\r
1362                         {0xCEu, 0x6Eu},\r
1363                         {0xD6u, 0x0Fu},\r
1364                         {0xD8u, 0x49u},\r
1365                         {0xE0u, 0x01u},\r
1366                         {0xE6u, 0x40u},\r
1367                         {0xEEu, 0x06u},\r
1368                         {0x83u, 0x01u},\r
1369                         {0x97u, 0x01u},\r
1370                         {0x9Cu, 0x02u},\r
1371                         {0x9Du, 0x20u},\r
1372                         {0xABu, 0x80u},\r
1373                         {0xB2u, 0x04u},\r
1374                         {0xB3u, 0x08u},\r
1375                         {0xB7u, 0x80u},\r
1376                         {0xEAu, 0xA0u},\r
1377                         {0xEEu, 0x12u},\r
1378                         {0xACu, 0x02u},\r
1379                         {0xB1u, 0x20u},\r
1380                         {0xE8u, 0x20u},\r
1381                         {0x12u, 0x08u},\r
1382                         {0x15u, 0x80u},\r
1383                         {0x17u, 0x01u},\r
1384                         {0x33u, 0x01u},\r
1385                         {0x36u, 0x88u},\r
1386                         {0x38u, 0x01u},\r
1387                         {0x39u, 0x80u},\r
1388                         {0x3Cu, 0x04u},\r
1389                         {0x3Du, 0x80u},\r
1390                         {0x43u, 0x10u},\r
1391                         {0x50u, 0x80u},\r
1392                         {0x5Au, 0x04u},\r
1393                         {0x5Du, 0x02u},\r
1394                         {0x61u, 0x20u},\r
1395                         {0x64u, 0x08u},\r
1396                         {0x89u, 0x40u},\r
1397                         {0x8Cu, 0x01u},\r
1398                         {0x8Du, 0x20u},\r
1399                         {0xC4u, 0xE0u},\r
1400                         {0xCCu, 0xE0u},\r
1401                         {0xCEu, 0xF0u},\r
1402                         {0xD0u, 0x10u},\r
1403                         {0xD4u, 0x20u},\r
1404                         {0xD6u, 0xC0u},\r
1405                         {0xD8u, 0xC0u},\r
1406                         {0x31u, 0x20u},\r
1407                         {0x32u, 0x04u},\r
1408                         {0x36u, 0x40u},\r
1409                         {0x37u, 0x04u},\r
1410                         {0x50u, 0x08u},\r
1411                         {0x51u, 0x01u},\r
1412                         {0x55u, 0x08u},\r
1413                         {0x5Du, 0x02u},\r
1414                         {0x81u, 0x02u},\r
1415                         {0x89u, 0x01u},\r
1416                         {0x94u, 0x04u},\r
1417                         {0x96u, 0x04u},\r
1418                         {0x9Cu, 0x08u},\r
1419                         {0x9Fu, 0x10u},\r
1420                         {0xA6u, 0x80u},\r
1421                         {0xACu, 0x80u},\r
1422                         {0xADu, 0x02u},\r
1423                         {0xCCu, 0xF0u},\r
1424                         {0xD4u, 0xE0u},\r
1425                         {0xD6u, 0x80u},\r
1426                         {0xE6u, 0x20u},\r
1427                         {0xEAu, 0x10u},\r
1428                         {0xEEu, 0x10u},\r
1429                         {0x12u, 0x80u},\r
1430                         {0x80u, 0x08u},\r
1431                         {0x86u, 0x04u},\r
1432                         {0x89u, 0x02u},\r
1433                         {0x8Cu, 0x08u},\r
1434                         {0x96u, 0x0Cu},\r
1435                         {0x9Cu, 0x08u},\r
1436                         {0x9Fu, 0x14u},\r
1437                         {0xA4u, 0x08u},\r
1438                         {0xA5u, 0x20u},\r
1439                         {0xA6u, 0xC0u},\r
1440                         {0xB4u, 0x04u},\r
1441                         {0xB5u, 0x08u},\r
1442                         {0xC4u, 0x10u},\r
1443                         {0xE2u, 0xC0u},\r
1444                         {0x63u, 0x08u},\r
1445                         {0x83u, 0x04u},\r
1446                         {0x85u, 0x20u},\r
1447                         {0x86u, 0x04u},\r
1448                         {0x87u, 0x08u},\r
1449                         {0x96u, 0x08u},\r
1450                         {0x9Du, 0x02u},\r
1451                         {0x9Fu, 0x14u},\r
1452                         {0xA5u, 0x20u},\r
1453                         {0xA6u, 0x40u},\r
1454                         {0xD8u, 0x40u},\r
1455                         {0xE2u, 0x90u},\r
1456                         {0xE6u, 0x50u},\r
1457                         {0x09u, 0x80u},\r
1458                         {0x0Eu, 0x80u},\r
1459                         {0x13u, 0x01u},\r
1460                         {0x50u, 0x80u},\r
1461                         {0x51u, 0x02u},\r
1462                         {0x54u, 0x04u},\r
1463                         {0x56u, 0x01u},\r
1464                         {0x8Fu, 0x01u},\r
1465                         {0xC2u, 0x06u},\r
1466                         {0xC4u, 0x08u},\r
1467                         {0xD4u, 0x07u},\r
1468                         {0xD6u, 0x04u},\r
1469                         {0xE6u, 0x08u},\r
1470                         {0x02u, 0x08u},\r
1471                         {0x05u, 0x40u},\r
1472                         {0x06u, 0x20u},\r
1473                         {0x08u, 0x24u},\r
1474                         {0x0Du, 0x08u},\r
1475                         {0x0Eu, 0x08u},\r
1476                         {0x84u, 0x20u},\r
1477                         {0x85u, 0x02u},\r
1478                         {0x88u, 0x04u},\r
1479                         {0x8Cu, 0x80u},\r
1480                         {0x8Du, 0x88u},\r
1481                         {0x9Eu, 0x21u},\r
1482                         {0xA1u, 0x80u},\r
1483                         {0xA4u, 0x84u},\r
1484                         {0xA5u, 0x02u},\r
1485                         {0xAAu, 0x20u},\r
1486                         {0xAEu, 0x40u},\r
1487                         {0xC0u, 0x07u},\r
1488                         {0xC2u, 0x0Fu},\r
1489                         {0xE2u, 0x08u},\r
1490                         {0xE4u, 0x02u},\r
1491                         {0xE6u, 0x09u},\r
1492                         {0x88u, 0x04u},\r
1493                         {0xA4u, 0x04u},\r
1494                         {0xAAu, 0x0Cu},\r
1495                         {0xB1u, 0x40u},\r
1496                         {0xB6u, 0x01u},\r
1497                         {0xE0u, 0x04u},\r
1498                         {0xEAu, 0x01u},\r
1499                         {0xECu, 0x02u},\r
1500                         {0x0Bu, 0x88u},\r
1501                         {0x0Fu, 0x41u},\r
1502                         {0x83u, 0x01u},\r
1503                         {0x87u, 0x44u},\r
1504                         {0xC2u, 0x0Fu},\r
1505                         {0x8Fu, 0x10u},\r
1506                         {0x9Du, 0x02u},\r
1507                         {0x9Fu, 0x10u},\r
1508                         {0xA3u, 0x08u},\r
1509                         {0xABu, 0x04u},\r
1510                         {0xAEu, 0x40u},\r
1511                         {0xEEu, 0x60u},\r
1512                         {0x05u, 0x02u},\r
1513                         {0x57u, 0x08u},\r
1514                         {0x5Du, 0x40u},\r
1515                         {0x91u, 0x40u},\r
1516                         {0x9Du, 0x02u},\r
1517                         {0xA3u, 0x08u},\r
1518                         {0xB5u, 0x40u},\r
1519                         {0xC0u, 0x20u},\r
1520                         {0xD4u, 0x40u},\r
1521                         {0xD6u, 0x20u},\r
1522                         {0xAFu, 0x40u},\r
1523                         {0x00u, 0x03u},\r
1524                         {0x08u, 0x03u},\r
1525                         {0x0Au, 0x03u},\r
1526                         {0x10u, 0x03u},\r
1527                         {0x1Au, 0x03u},\r
1528                         {0x00u, 0xFDu},\r
1529                         {0x01u, 0xABu},\r
1530                         {0x02u, 0x02u},\r
1531                         {0x10u, 0x55u},\r
1532                 };\r
1533 \r
1534 \r
1535 \r
1536                 CYPACKED typedef struct {\r
1537                         void CYFAR *address;\r
1538                         uint16 size;\r
1539                 } CYPACKED_ATTR cfg_memset_t;\r
1540 \r
1541 \r
1542                 CYPACKED typedef struct {\r
1543                         void CYFAR *dest;\r
1544                         const void CYCODE *src;\r
1545                         uint16 size;\r
1546                 } CYPACKED_ATTR cfg_memcpy_t;\r
1547 \r
1548                 static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
1549                         /* address, size */\r
1550                         {(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
1551                         {(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
1552                         {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1024u},\r
1553                         {(void CYFAR *)(CYDEV_UCFG_B0_P2_U1_BASE), 2944u},\r
1554                         {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
1555                         {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
1556                         {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
1557                         {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},\r
1558                 };\r
1559 \r
1560                 /* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */\r
1561                 static const uint8 CYCODE BS_UDB_1_3_0_CONFIG_VAL[] = {\r
1562                         0x8Du, 0x00u, 0x00u, 0x00u, 0x8Du, 0x09u, 0x00u, 0x12u, 0x8Du, 0x00u, 0x00u, 0x01u, 0x0Du, 0x00u, 0x80u, 0x30u, \r
1563                         0x02u, 0x00u, 0x0Du, 0x00u, 0x00u, 0x00u, 0x80u, 0x09u, 0x12u, 0x00u, 0x44u, 0x06u, 0x60u, 0x00u, 0x00u, 0x08u, \r
1564                         0x8Du, 0x09u, 0x00u, 0x24u, 0x00u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x18u, 0x00u, 0x11u, 0x00u, 0x22u, 0x00u, \r
1565                         0x0Fu, 0x38u, 0x00u, 0x00u, 0x80u, 0x07u, 0x70u, 0x00u, 0x80u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, \r
1566                         0x26u, 0x05u, 0x40u, 0x00u, 0x03u, 0xBEu, 0xFBu, 0xDCu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
1567                         0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x10u, 0x00u, 0x00u, 0x01u, \r
1568                         0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
1569                         0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
1570 \r
1571                 static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
1572                         /* dest, src, size */\r
1573                         {(void CYFAR *)(CYDEV_UCFG_B0_P2_U0_BASE), BS_UDB_1_3_0_CONFIG_VAL, 128u},\r
1574                 };\r
1575 \r
1576                 uint8 CYDATA i;\r
1577 \r
1578                 /* Zero out critical memory blocks before beginning configuration */\r
1579                 for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)\r
1580                 {\r
1581                         const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];\r
1582                         CYMEMZERO(ms->address, (uint32)(ms->size));\r
1583                 }\r
1584 \r
1585                 /* Copy device configuration data into registers */\r
1586                 for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)\r
1587                 {\r
1588                         const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];\r
1589                         void * CYDATA destPtr = mc->dest;\r
1590                         const void CYCODE * CYDATA srcPtr = mc->src;\r
1591                         uint16 CYDATA numBytes = mc->size;\r
1592                         CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);\r
1593                 }\r
1594 \r
1595                 cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);\r
1596 \r
1597                 /* Perform normal device configuration. Order is not critical for these items. */\r
1598                 CYMEMZERO((void CYFAR *)(CYREG_PHUB_CFGMEM0_CFG0), 4u);\r
1599                 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM1_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM1_VAL), 4u);\r
1600                 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM2_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM2_VAL), 4u);\r
1601                 CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM3_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM3_VAL), 4u);\r
1602 \r
1603                 /* Enable digital routing */\r
1604                 CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);\r
1605                 CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);\r
1606 \r
1607                 /* Enable UDB array */\r
1608                 CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u);\r
1609                 CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);\r
1610         }\r
1611 \r
1612         /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */\r
1613         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u);\r
1614         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR), (const void CYCODE *)(BS_IOPINS0_7_VAL), 10u);\r
1615         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR + 0x0000000Bu), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u);\r
1616         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u);\r
1617         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u);\r
1618         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DR), (const void CYCODE *)(BS_IOPINS0_3_VAL), 10u);\r
1619         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);\r
1620         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT5_DM0), (const void CYCODE *)(BS_IOPINS0_5_VAL), 8u);\r
1621         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u);\r
1622 \r
1623         /* Switch Boost to the precision bandgap reference from its internal reference */\r
1624         CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));\r
1625 \r
1626         /* Perform basic analog initialization to defaults */\r
1627         AnalogSetDefault();\r
1628 \r
1629         /* Configure alternate active mode */\r
1630         CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u);\r
1631 }\r