Fix DMA transfer bug.
[SCSI2SD.git] / software / SCSI2SD / SCSI2SD.cydsn / SCSI2SD.cycdx
1 <?xml version="1.0" encoding="utf-8"?>\r
2 <blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
3   <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
4     <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006577" bitWidth="8" desc="" />\r
5   </block>\r
6   <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
7     <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />\r
8   </block>\r
9   <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
10   <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
11     <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
12     <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
13     <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
14     <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
15     <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
16     <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
17     <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">\r
18       <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />\r
19     </register>\r
20     <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">\r
21       <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />\r
22       <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">\r
23         <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />\r
24         <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />\r
25       </field>\r
26       <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />\r
27       <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />\r
28       <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />\r
29       <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">\r
30         <value name="Timer" value="0" desc="CMP and TC are output." />\r
31         <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />\r
32       </field>\r
33       <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />\r
34     </register>\r
35     <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">\r
36       <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />\r
37       <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">\r
38         <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />\r
39         <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />\r
40       </field>\r
41       <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />\r
42       <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />\r
43       <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />\r
44       <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />\r
45     </register>\r
46     <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">\r
47       <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">\r
48         <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />\r
49         <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />\r
50         <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />\r
51         <value name="Irq" value="11" desc="Timer runs until IRQ." />\r
52       </field>\r
53       <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />\r
54       <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />\r
55       <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">\r
56         <value name="Equal" value="0" desc="Compare Equal " />\r
57         <value name="Less than" value="1" desc="Compare Less Than " />\r
58         <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />\r
59         <value name="Greater" value="11" desc="Compare Greater Than ." />\r
60         <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />\r
61       </field>\r
62       <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />\r
63     </register>\r
64     <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />\r
65     <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />\r
66   </block>\r
67   <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
68   <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
69   <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
70     <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
71     <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
72     <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
73     <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
74     <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
75   </block>\r
76   <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
77   <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
78     <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
79     <block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
80     <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
81     <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
82     <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
83     <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
84     <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
85     <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
86     <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
87     <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
88     <block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
89     <block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
90     <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
91     <register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0">\r
92       <field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />\r
93       <field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />\r
94       <field name="fsusbio_pd_pullup_n" from="2" to="2" access="RW" resetVal="" desc="" />\r
95     </register>\r
96     <register name="USBFS_PM_ACT_CFG" address="0x400043A5" bitWidth="8" desc="Active Power Mode Configuration Register" />\r
97     <register name="USBFS_PM_STBY_CFG" address="0x400043B5" bitWidth="8" desc="Standby Power Mode Configuration Register" />\r
98     <register name="USBFS_PRT.PS" address="0x400051F1" bitWidth="8" desc="Port Pin State Register">\r
99       <field name="PinState_DP" from="6" to="6" access="R" resetVal="" desc="" />\r
100       <field name="PinState_DM" from="7" to="7" access="R" resetVal="" desc="" />\r
101     </register>\r
102     <register name="USBFS_PRT_DM0" address="0x400051F2" bitWidth="8" desc="Port Drive Mode Register">\r
103       <field name="DriveMode_DP" from="6" to="6" access="RW" resetVal="" desc="" />\r
104       <field name="DriveMode_DM" from="7" to="7" access="RW" resetVal="" desc="" />\r
105     </register>\r
106     <register name="USBFS_PRT_DM1" address="0x400051F3" bitWidth="8" desc="Port Drive Mode Register">\r
107       <field name="PullUp_en_DP" from="6" to="6" access="RW" resetVal="" desc="" />\r
108       <field name="PullUp_en_DM" from="7" to="7" access="RW" resetVal="" desc="" />\r
109     </register>\r
110     <register name="USBFS_PRT.INP_DIS" address="0x400051F8" bitWidth="8" desc="Input buffer disable override">\r
111       <field name="seinput_dis_dp" from="6" to="6" access="RW" resetVal="" desc="" />\r
112       <field name="seinput_dis_dm" from="7" to="7" access="RW" resetVal="" desc="" />\r
113     </register>\r
114     <register name="USBFS_EP0_DR0" address="0x40006000" bitWidth="8" desc="bmRequestType" />\r
115     <register name="USBFS_EP0_DR1" address="0x40006001" bitWidth="8" desc="bRequest" />\r
116     <register name="USBFS_EP0_DR2" address="0x40006002" bitWidth="8" desc="wValueLo" />\r
117     <register name="USBFS_EP0_DR3" address="0x40006003" bitWidth="8" desc="wValueHi" />\r
118     <register name="USBFS_EP0_DR4" address="0x40006004" bitWidth="8" desc="wIndexLo" />\r
119     <register name="USBFS_EP0_DR5" address="0x40006005" bitWidth="8" desc="wIndexHi" />\r
120     <register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" />\r
121     <register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" />\r
122     <register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0">\r
123       <field name="device_address" from="0" to="6" access="R" resetVal="" desc="" />\r
124       <field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />\r
125     </register>\r
126     <register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1">\r
127       <field name="reg_enable" from="0" to="0" access="RW" resetVal="" desc="" />\r
128       <field name="enable_lock" from="1" to="1" access="RW" resetVal="" desc="" />\r
129       <field name="bus_activity" from="2" to="2" access="RW" resetVal="" desc="" />\r
130       <field name="trim_offset_msb" from="3" to="3" access="RW" resetVal="" desc="" />\r
131     </register>\r
132     <register name="USBFS_SIE_EP1_CR0" address="0x4000600E" bitWidth="8" desc="The Endpoint1 Control Register" />\r
133     <register name="USBFS_USBIO_CR0" address="0x40006010" bitWidth="8" desc="USBIO Control Register 0">\r
134       <field name="rd" from="0" to="0" access="R" resetVal="" desc="" />\r
135       <field name="td" from="5" to="5" access="RW" resetVal="" desc="" />\r
136       <field name="tse0" from="6" to="6" access="RW" resetVal="" desc="" />\r
137       <field name="ten" from="7" to="7" access="RW" resetVal="" desc="" />\r
138     </register>\r
139     <register name="USBFS_USBIO_CR1" address="0x40006012" bitWidth="8" desc="USBIO Control Register 1">\r
140       <field name="dmo" from="0" to="0" access="R" resetVal="" desc="" />\r
141       <field name="dpo" from="1" to="1" access="R" resetVal="" desc="" />\r
142       <field name="usbpuen" from="2" to="2" access="RW" resetVal="" desc="" />\r
143       <field name="iomode" from="5" to="5" access="RW" resetVal="" desc="" />\r
144     </register>\r
145     <register name="USBFS_SIE_EP2_CR0" address="0x4000601E" bitWidth="8" desc="The Endpoint2 Control Register" />\r
146     <register name="USBFS_SIE_EP3_CR0" address="0x4000602E" bitWidth="8" desc="The Endpoint3 Control Register" />\r
147     <register name="USBFS_SIE_EP4_CR0" address="0x4000603E" bitWidth="8" desc="The Endpoint4 Control Register" />\r
148     <register name="USBFS_SIE_EP5_CR0" address="0x4000604E" bitWidth="8" desc="The Endpoint5 Control Register" />\r
149     <register name="USBFS_SIE_EP6_CR0" address="0x4000605E" bitWidth="8" desc="The Endpoint6 Control Register" />\r
150     <register name="USBFS_SIE_EP7_CR0" address="0x4000606E" bitWidth="8" desc="The Endpoint7 Control Register" />\r
151     <register name="USBFS_SIE_EP8_CR0" address="0x4000607E" bitWidth="8" desc="The Endpoint8 Control Register" />\r
152     <register name="USBFS_BUF_SIZE" address="0x4000608C" bitWidth="8" desc="Dedicated Endpoint Buffer Size Register" />\r
153     <register name="USBFS_EP_ACTIVE" address="0x4000608E" bitWidth="8" desc="Endpoint Active Indication Register" />\r
154     <register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />\r
155     <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />\r
156   </block>\r
157   <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
158   <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
159   <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
160   <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
161   <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
162   <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
163   <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
164   <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
165   <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
166   <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
167   <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
168   <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
169     <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" />\r
170   </block>\r
171   <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
172   <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
173   <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
174   <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
175   <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
176   <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
177   <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
178   <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
179   <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
180   <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
181   <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
182   <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
183   <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
184   <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
185   <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
186   <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
187   <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
188   <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
189 </blockRegMap>