0a7fae956b447194190f27449b858557dda4ce98
[SCSI2SD.git] / software / SCSI2SD / pbook / pbook.cydsn / Generated_Source / PSoC5 / cyfitter_cfg.c
1 /*******************************************************************************
2 * FILENAME: cyfitter_cfg.c
3 * PSoC Creator 3.0 Component Pack 7
4 *
5 * Description:
6 * This file is automatically generated by PSoC Creator with device 
7 * initialization code.  Except for the user defined sections in
8 * CyClockStartupError(), this file should not be modified.
9 *
10 ********************************************************************************
11 * Copyright 2013, Cypress Semiconductor Corporation.  All rights reserved.
12 * You may use this file only in accordance with the license, terms, conditions, 
13 * disclaimers, and limitations in the end user license agreement accompanying 
14 * the software package with which this file was provided.
15 ********************************************************************************/
16
17 #include <string.h>
18 #include <cytypes.h>
19 #include <cydevice_trm.h>
20 #include <cyfitter.h>
21 #include <CyLib.h>
22 #include <cyfitter_cfg.h>
23
24 #define CY_NEED_CYCLOCKSTARTUPERROR 1
25
26
27 #if defined(__GNUC__) || defined(__ARMCC_VERSION)
28     #define CYPACKED 
29     #define CYPACKED_ATTR __attribute__ ((packed))
30     #define CYALIGNED __attribute__ ((aligned))
31     #define CY_CFG_UNUSED __attribute__ ((unused))
32     #define CY_CFG_SECTION __attribute__ ((section(".psocinit")))
33     
34     #if defined(__ARMCC_VERSION)
35         #define CY_CFG_MEMORY_BARRIER() __memory_changed()
36     #else
37         #define CY_CFG_MEMORY_BARRIER() __sync_synchronize()
38     #endif
39     
40 #elif defined(__ICCARM__)
41     #include <intrinsics.h>
42
43     #define CYPACKED __packed
44     #define CYPACKED_ATTR 
45     #define CYALIGNED _Pragma("data_alignment=4")
46     #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177")
47     #define CY_CFG_SECTION _Pragma("location=\".psocinit\"")
48     
49     #define CY_CFG_MEMORY_BARRIER() __DMB()
50     
51 #else
52     #error Unsupported toolchain
53 #endif
54
55
56 CY_CFG_UNUSED
57 static void CYMEMZERO(void *s, size_t n);
58 CY_CFG_UNUSED
59 static void CYMEMZERO(void *s, size_t n)
60 {
61         (void)memset(s, 0, n);
62 }
63 CY_CFG_UNUSED
64 static void CYCONFIGCPY(void *dest, const void *src, size_t n);
65 CY_CFG_UNUSED
66 static void CYCONFIGCPY(void *dest, const void *src, size_t n)
67 {
68         (void)memcpy(dest, src, n);
69 }
70 CY_CFG_UNUSED
71 static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);
72 CY_CFG_UNUSED
73 static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
74 {
75         (void)memcpy(dest, src, n);
76 }
77
78
79
80 /* Clock startup error codes                                                   */
81 #define CYCLOCKSTART_NO_ERROR    0u
82 #define CYCLOCKSTART_XTAL_ERROR  1u
83 #define CYCLOCKSTART_32KHZ_ERROR 2u
84 #define CYCLOCKSTART_PLL_ERROR   3u
85
86 #ifdef CY_NEED_CYCLOCKSTARTUPERROR
87 /*******************************************************************************
88 * Function Name: CyClockStartupError
89 ********************************************************************************
90 * Summary:
91 *  If an error is encountered during clock configuration (crystal startup error,
92 *  PLL lock error, etc.), the system will end up here.  Unless reimplemented by
93 *  the customer, this function will stop in an infinite loop.
94 *
95 * Parameters:
96 *   void
97 *
98 * Return:
99 *   void
100 *
101 *******************************************************************************/
102 CY_CFG_UNUSED
103 static void CyClockStartupError(uint8 errorCode);
104 CY_CFG_UNUSED
105 static void CyClockStartupError(uint8 errorCode)
106 {
107     /* To remove the compiler warning if errorCode not used.                */
108     errorCode = errorCode;
109
110     /* `#START CyClockStartupError` */
111
112     /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.),  */
113     /* we will end up here to allow the customer to implement something to  */
114     /* deal with the clock condition.                                       */
115
116     /* `#END` */
117
118     /* If nothing else, stop here since the clocks have not started         */
119     /* correctly.                                                           */
120     while(1) {}
121 }
122 #endif
123
124 #define CY_CFG_BASE_ADDR_COUNT 32u
125 CYPACKED typedef struct
126 {
127         uint8 offset;
128         uint8 value;
129 } CYPACKED_ATTR cy_cfg_addrvalue_t;
130
131
132
133 /*******************************************************************************
134 * Function Name: cfg_write_bytes32
135 ********************************************************************************
136 * Summary:
137 *  This function is used for setting up the chip configuration areas that
138 *  contain relatively sparse data.
139 *
140 * Parameters:
141 *   void
142 *
143 * Return:
144 *   void
145 *
146 *******************************************************************************/
147 static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]);
148 static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[])
149 {
150         /* For 32-bit little-endian architectures */
151         uint32 i, j = 0u;
152         for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++)
153         {
154                 uint32 baseAddr = addr_table[i];
155                 uint8 count = (uint8)baseAddr;
156                 baseAddr &= 0xFFFFFF00u;
157                 while (count != 0u)
158                 {
159                         CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value);
160                         j++;
161                         count--;
162                 }
163         }
164 }
165
166 /*******************************************************************************
167 * Function Name: ClockSetup
168 ********************************************************************************
169 *
170 * Summary:
171 *  Performs the initialization of all of the clocks in the device based on the
172 *  settings in the Clock tab of the DWR.  This includes enabling the requested
173 *  clocks and setting the necessary dividers to produce the desired frequency. 
174 *
175 * Parameters:
176 *  void
177 *
178 * Return:
179 *  void
180 *
181 *******************************************************************************/
182 static void ClockSetup(void);
183 static void ClockSetup(void)
184 {
185         uint32 timeout;
186         uint8 pllLock;
187
188
189         /* Configure Digital Clocks based on settings from Clock DWR */
190         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0001u);
191         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x10u);
192         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x001Du);
193         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x19u);
194
195         /* Configure ILO based on settings from Clock DWR */
196         CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);
197
198         /* Configure IMO based on settings from Clock DWR */
199         CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u);
200         CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB)));
201
202         /* Configure PLL based on settings from Clock DWR */
203         CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0919u);
204         CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);
205         /* Wait up to 250us for the PLL to lock */
206         pllLock = 0u;
207         for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--)
208         { 
209                 pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0));
210                 CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */
211         }
212         /* If we ran out of time the PLL didn't lock so go to the error function */
213         if (timeout == 0u)
214         {
215                 CyClockStartupError(CYCLOCKSTART_PLL_ERROR);
216         }
217
218         /* Configure Bus/Master Clock based on settings from Clock DWR */
219         CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u);
220         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u);
221         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u);
222         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u);
223         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u);
224
225         /* Configure USB Clock based on settings from Clock DWR */
226         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);
227         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);
228
229         CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x02u)));
230 }
231
232
233 /* Analog API Functions */
234
235
236 /*******************************************************************************
237 * Function Name: AnalogSetDefault
238 ********************************************************************************
239 *
240 * Summary:
241 *  Sets up the analog portions of the chip to default values based on chip
242 *  configuration options from the project.
243 *
244 * Parameters:
245 *  void
246 *
247 * Return:
248 *  void
249 *
250 *******************************************************************************/
251 static void AnalogSetDefault(void);
252 static void AnalogSetDefault(void)
253 {
254         uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u));
255         CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u));
256         CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu));
257         CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);
258 }
259
260
261 /*******************************************************************************
262 * Function Name: SetAnalogRoutingPumps
263 ********************************************************************************
264 *
265 * Summary:
266 * Enables or disables the analog pumps feeding analog routing switches.
267 * Intended to be called at startup, based on the Vdda system configuration;
268 * may be called during operation when the user informs us that the Vdda voltage
269 * crossed the pump threshold.
270 *
271 * Parameters:
272 *  enabled - 1 to enable the pumps, 0 to disable the pumps
273 *
274 * Return:
275 *  void
276 *
277 *******************************************************************************/
278 void SetAnalogRoutingPumps(uint8 enabled)
279 {
280         uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0);
281         if (enabled != 0u)
282         {
283                 regValue |= 0x00u;
284         }
285         else
286         {
287                 regValue &= (uint8)~0x00u;
288         }
289         CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue);
290 }
291
292 #define CY_AMUX_UNUSED CYREG_BOOST_SR
293
294
295 /*******************************************************************************
296 * Function Name: cyfitter_cfg
297 ********************************************************************************
298 * Summary:
299 *  This function is called by the start-up code for the selected device. It
300 *  performs all of the necessary device configuration based on the design
301 *  settings.  This includes settings from the Design Wide Resources (DWR) such
302 *  as Clocks and Pins as well as any component configuration that is necessary.
303 *
304 * Parameters:  
305 *   void
306 *
307 * Return:
308 *   void
309 *
310 *******************************************************************************/
311
312 void cyfitter_cfg(void)
313 {
314         /* IOPINS0_0 Address: CYREG_PRT0_DR Size (bytes): 10 */
315         static const uint8 CYCODE BS_IOPINS0_0_VAL[] = {
316                 0x02u, 0x00u, 0x30u, 0xCCu, 0xCEu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x01u};
317
318         /* IOPINS0_7 Address: CYREG_PRT12_DM0 Size (bytes): 8 */
319         static const uint8 CYCODE BS_IOPINS0_7_VAL[] = {
320                 0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
321
322         /* IOPINS1_7 Address: CYREG_PRT12_DM0 + 0x00000009u Size (bytes): 5 */
323         static const uint8 CYCODE BS_IOPINS1_7_VAL[] = {
324                 0x00u, 0x00u, 0x00u, 0x00u, 0x10u};
325
326         /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */
327         static const uint8 CYCODE BS_IOPINS0_8_VAL[] = {
328                 0x00u, 0x00u, 0x00u, 0x30u, 0x30u, 0x00u, 0x20u, 0x00u, 0xC0u, 0x00u};
329
330         /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */
331         static const uint8 CYCODE BS_IOPINS0_2_VAL[] = {
332                 0x33u, 0xCCu, 0xCCu, 0x00u, 0xCCu, 0x00u, 0x00u, 0x01u};
333
334         /* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */
335         static const uint8 CYCODE BS_IOPINS0_3_VAL[] = {
336                 0x00u, 0x3Eu, 0x00u, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u};
337
338         /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */
339         static const uint8 CYCODE BS_IOPINS0_4_VAL[] = {
340                 0xCCu, 0x30u, 0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u};
341
342         /* IOPINS0_5 Address: CYREG_PRT5_DM0 Size (bytes): 8 */
343         static const uint8 CYCODE BS_IOPINS0_5_VAL[] = {
344                 0x0Cu, 0x03u, 0x03u, 0x00u, 0x03u, 0x00u, 0x00u, 0x01u};
345
346         /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */
347         static const uint8 CYCODE BS_IOPINS0_6_VAL[] = {
348                 0xCCu, 0x33u, 0x33u, 0x00u, 0x30u, 0x00u, 0x00u, 0x01u};
349
350 #ifdef CYGlobalIntDisable
351         /* Disable interrupts by default. Let user enable if/when they want. */
352         CYGlobalIntDisable
353 #endif
354
355
356         /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
357         CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u));
358         /* Setup clocks based on selections from Clock DWR */
359         ClockSetup();
360         /* Enable/Disable Debug functionality based on settings from System DWR */
361         CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u));
362
363         {
364                 static const uint32 CYCODE cy_cfg_addr_table[] = {
365                         0x40004502u, /* Base address: 0x40004500 Count: 2 */
366                         0x4000520Au, /* Base address: 0x40005200 Count: 10 */
367                         0x40006402u, /* Base address: 0x40006400 Count: 2 */
368                         0x40010442u, /* Base address: 0x40010400 Count: 66 */
369                         0x40010534u, /* Base address: 0x40010500 Count: 52 */
370                         0x40010648u, /* Base address: 0x40010600 Count: 72 */
371                         0x40010740u, /* Base address: 0x40010700 Count: 64 */
372                         0x40010908u, /* Base address: 0x40010900 Count: 8 */
373                         0x40010A38u, /* Base address: 0x40010A00 Count: 56 */
374                         0x40010B53u, /* Base address: 0x40010B00 Count: 83 */
375                         0x40010C40u, /* Base address: 0x40010C00 Count: 64 */
376                         0x40010D3Eu, /* Base address: 0x40010D00 Count: 62 */
377                         0x40010E47u, /* Base address: 0x40010E00 Count: 71 */
378                         0x40010F29u, /* Base address: 0x40010F00 Count: 41 */
379                         0x40011503u, /* Base address: 0x40011500 Count: 3 */
380                         0x4001160Cu, /* Base address: 0x40011600 Count: 12 */
381                         0x40011749u, /* Base address: 0x40011700 Count: 73 */
382                         0x40011903u, /* Base address: 0x40011900 Count: 3 */
383                         0x40014005u, /* Base address: 0x40014000 Count: 5 */
384                         0x40014107u, /* Base address: 0x40014100 Count: 7 */
385                         0x40014208u, /* Base address: 0x40014200 Count: 8 */
386                         0x40014302u, /* Base address: 0x40014300 Count: 2 */
387                         0x4001440Eu, /* Base address: 0x40014400 Count: 14 */
388                         0x40014517u, /* Base address: 0x40014500 Count: 23 */
389                         0x4001460Au, /* Base address: 0x40014600 Count: 10 */
390                         0x4001470Au, /* Base address: 0x40014700 Count: 10 */
391                         0x40014809u, /* Base address: 0x40014800 Count: 9 */
392                         0x4001490Bu, /* Base address: 0x40014900 Count: 11 */
393                         0x40014C07u, /* Base address: 0x40014C00 Count: 7 */
394                         0x40014D0Au, /* Base address: 0x40014D00 Count: 10 */
395                         0x40015006u, /* Base address: 0x40015000 Count: 6 */
396                         0x40015101u, /* Base address: 0x40015100 Count: 1 */
397                 };
398
399                 static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
400                         {0x27u, 0x02u},
401                         {0x7Eu, 0x02u},
402                         {0x00u, 0x04u},
403                         {0x01u, 0x0Cu},
404                         {0x10u, 0x0Cu},
405                         {0x11u, 0x84u},
406                         {0x18u, 0x04u},
407                         {0x1Cu, 0x20u},
408                         {0x29u, 0x02u},
409                         {0x31u, 0x10u},
410                         {0x78u, 0x20u},
411                         {0x7Cu, 0x40u},
412                         {0x3Au, 0x03u},
413                         {0x86u, 0x0Fu},
414                         {0x03u, 0x04u},
415                         {0x04u, 0x01u},
416                         {0x05u, 0x04u},
417                         {0x07u, 0x02u},
418                         {0x09u, 0x04u},
419                         {0x0Bu, 0x01u},
420                         {0x13u, 0x03u},
421                         {0x17u, 0x04u},
422                         {0x24u, 0x01u},
423                         {0x31u, 0x07u},
424                         {0x32u, 0x01u},
425                         {0x38u, 0x08u},
426                         {0x58u, 0x0Bu},
427                         {0x59u, 0x04u},
428                         {0x5Bu, 0x04u},
429                         {0x5Cu, 0x99u},
430                         {0x5Fu, 0x01u},
431                         {0x80u, 0x17u},
432                         {0x81u, 0x01u},
433                         {0x82u, 0x28u},
434                         {0x84u, 0x20u},
435                         {0x86u, 0xD0u},
436                         {0x88u, 0x29u},
437                         {0x89u, 0x01u},
438                         {0x8Au, 0x46u},
439                         {0x8Du, 0x01u},
440                         {0x90u, 0xD6u},
441                         {0x91u, 0x01u},
442                         {0x94u, 0x02u},
443                         {0x95u, 0x01u},
444                         {0x98u, 0xD2u},
445                         {0x99u, 0x22u},
446                         {0x9Au, 0x04u},
447                         {0x9Bu, 0x08u},
448                         {0x9Cu, 0x04u},
449                         {0x9Du, 0x07u},
450                         {0x9Fu, 0x18u},
451                         {0xA0u, 0xD6u},
452                         {0xA1u, 0x10u},
453                         {0xA3u, 0x40u},
454                         {0xA4u, 0xD0u},
455                         {0xA5u, 0x08u},
456                         {0xA6u, 0x06u},
457                         {0xA7u, 0x21u},
458                         {0xA8u, 0x21u},
459                         {0xA9u, 0x04u},
460                         {0xAAu, 0x8Eu},
461                         {0xACu, 0xD6u},
462                         {0xB0u, 0x01u},
463                         {0xB2u, 0xF0u},
464                         {0xB4u, 0x0Fu},
465                         {0xB5u, 0x3Fu},
466                         {0xB6u, 0x08u},
467                         {0xB7u, 0x40u},
468                         {0xB8u, 0x20u},
469                         {0xB9u, 0x20u},
470                         {0xBAu, 0x08u},
471                         {0xBEu, 0x41u},
472                         {0xBFu, 0x10u},
473                         {0xD4u, 0x09u},
474                         {0xD8u, 0x0Bu},
475                         {0xD9u, 0x0Bu},
476                         {0xDBu, 0x0Bu},
477                         {0xDCu, 0x99u},
478                         {0xDDu, 0x90u},
479                         {0xDFu, 0x01u},
480                         {0x00u, 0x04u},
481                         {0x05u, 0x14u},
482                         {0x07u, 0x40u},
483                         {0x0Cu, 0x01u},
484                         {0x0Eu, 0x28u},
485                         {0x0Fu, 0x02u},
486                         {0x12u, 0x20u},
487                         {0x16u, 0x02u},
488                         {0x17u, 0x25u},
489                         {0x19u, 0x08u},
490                         {0x1Bu, 0x08u},
491                         {0x1Du, 0x14u},
492                         {0x1Fu, 0x61u},
493                         {0x21u, 0x02u},
494                         {0x25u, 0x80u},
495                         {0x26u, 0x20u},
496                         {0x2Fu, 0xA8u},
497                         {0x31u, 0x0Au},
498                         {0x34u, 0x01u},
499                         {0x36u, 0x05u},
500                         {0x37u, 0x60u},
501                         {0x38u, 0x20u},
502                         {0x39u, 0x04u},
503                         {0x3Au, 0x01u},
504                         {0x3Du, 0xA0u},
505                         {0x3Eu, 0x02u},
506                         {0x4Bu, 0xC0u},
507                         {0x5Cu, 0x01u},
508                         {0x5Du, 0x10u},
509                         {0x5Fu, 0x44u},
510                         {0x67u, 0x02u},
511                         {0x69u, 0x40u},
512                         {0x7Au, 0x80u},
513                         {0x7Eu, 0x80u},
514                         {0x80u, 0x40u},
515                         {0x85u, 0x0Cu},
516                         {0x8Cu, 0x10u},
517                         {0x8Du, 0x02u},
518                         {0x8Fu, 0x04u},
519                         {0xC0u, 0x74u},
520                         {0xC2u, 0xF0u},
521                         {0xC4u, 0xF4u},
522                         {0xCAu, 0xE0u},
523                         {0xCCu, 0xF3u},
524                         {0xCEu, 0xB7u},
525                         {0xD6u, 0xF0u},
526                         {0xD8u, 0x10u},
527                         {0xDEu, 0x81u},
528                         {0xE0u, 0x20u},
529                         {0xE2u, 0x42u},
530                         {0xE6u, 0x06u},
531                         {0xEEu, 0x02u},
532                         {0x01u, 0x08u},
533                         {0x02u, 0x9Fu},
534                         {0x03u, 0x20u},
535                         {0x05u, 0xD4u},
536                         {0x06u, 0x60u},
537                         {0x07u, 0x08u},
538                         {0x09u, 0x90u},
539                         {0x0Au, 0xFFu},
540                         {0x0Bu, 0x4Cu},
541                         {0x0Cu, 0xC0u},
542                         {0x0Du, 0xDCu},
543                         {0x0Eu, 0x01u},
544                         {0x10u, 0x1Fu},
545                         {0x11u, 0xDCu},
546                         {0x12u, 0x20u},
547                         {0x14u, 0x80u},
548                         {0x15u, 0x44u},
549                         {0x18u, 0xC0u},
550                         {0x1Au, 0x04u},
551                         {0x1Bu, 0x4Fu},
552                         {0x1Cu, 0xC0u},
553                         {0x1Du, 0x61u},
554                         {0x1Eu, 0x02u},
555                         {0x1Fu, 0x02u},
556                         {0x20u, 0x90u},
557                         {0x22u, 0x40u},
558                         {0x24u, 0xC0u},
559                         {0x25u, 0x21u},
560                         {0x26u, 0x08u},
561                         {0x27u, 0x0Eu},
562                         {0x28u, 0x7Fu},
563                         {0x2Au, 0x80u},
564                         {0x2Bu, 0x10u},
565                         {0x2Du, 0x4Cu},
566                         {0x2Fu, 0x90u},
567                         {0x31u, 0x0Fu},
568                         {0x33u, 0x61u},
569                         {0x34u, 0xFFu},
570                         {0x35u, 0x10u},
571                         {0x37u, 0x80u},
572                         {0x3Bu, 0x0Cu},
573                         {0x3Eu, 0x10u},
574                         {0x3Fu, 0x50u},
575                         {0x56u, 0x02u},
576                         {0x57u, 0x28u},
577                         {0x58u, 0x04u},
578                         {0x59u, 0x0Bu},
579                         {0x5Bu, 0x0Bu},
580                         {0x5Cu, 0x90u},
581                         {0x5Du, 0x90u},
582                         {0x5Fu, 0x01u},
583                         {0x85u, 0x04u},
584                         {0x87u, 0x02u},
585                         {0x89u, 0x04u},
586                         {0x8Bu, 0x01u},
587                         {0x8Eu, 0x02u},
588                         {0x8Fu, 0x04u},
589                         {0x92u, 0x01u},
590                         {0x97u, 0x03u},
591                         {0xA3u, 0x04u},
592                         {0xACu, 0x01u},
593                         {0xAEu, 0x02u},
594                         {0xB3u, 0x07u},
595                         {0xB6u, 0x03u},
596                         {0xBEu, 0x40u},
597                         {0xD6u, 0x08u},
598                         {0xD8u, 0x04u},
599                         {0xD9u, 0x04u},
600                         {0xDBu, 0x04u},
601                         {0xDCu, 0x90u},
602                         {0xDDu, 0x90u},
603                         {0xDFu, 0x01u},
604                         {0x01u, 0x80u},
605                         {0x05u, 0x38u},
606                         {0x06u, 0x82u},
607                         {0x08u, 0x21u},
608                         {0x09u, 0x20u},
609                         {0x0Cu, 0x04u},
610                         {0x0Du, 0x02u},
611                         {0x0Eu, 0x2Au},
612                         {0x11u, 0x40u},
613                         {0x17u, 0x25u},
614                         {0x19u, 0x40u},
615                         {0x1Cu, 0x04u},
616                         {0x21u, 0x08u},
617                         {0x24u, 0x03u},
618                         {0x25u, 0x22u},
619                         {0x27u, 0x60u},
620                         {0x2Au, 0x01u},
621                         {0x2Fu, 0x2Au},
622                         {0x31u, 0x08u},
623                         {0x34u, 0x04u},
624                         {0x36u, 0x01u},
625                         {0x37u, 0x60u},
626                         {0x38u, 0x60u},
627                         {0x39u, 0x04u},
628                         {0x3Au, 0x10u},
629                         {0x3Cu, 0x80u},
630                         {0x3Eu, 0x14u},
631                         {0x3Fu, 0x02u},
632                         {0x59u, 0x40u},
633                         {0x62u, 0x80u},
634                         {0x67u, 0x20u},
635                         {0x6Cu, 0x80u},
636                         {0x6Du, 0x80u},
637                         {0x6Eu, 0x1Eu},
638                         {0x6Fu, 0x07u},
639                         {0x74u, 0x40u},
640                         {0x76u, 0x02u},
641                         {0x7Eu, 0x80u},
642                         {0x90u, 0x60u},
643                         {0x91u, 0x44u},
644                         {0x94u, 0x05u},
645                         {0x97u, 0x04u},
646                         {0x99u, 0x18u},
647                         {0x9Au, 0x01u},
648                         {0x9Eu, 0x02u},
649                         {0x9Fu, 0x65u},
650                         {0xA1u, 0x80u},
651                         {0xA3u, 0x20u},
652                         {0xA5u, 0x50u},
653                         {0xA6u, 0x95u},
654                         {0xA7u, 0x85u},
655                         {0xAAu, 0x01u},
656                         {0xB1u, 0x10u},
657                         {0xB3u, 0x01u},
658                         {0xC0u, 0xF1u},
659                         {0xC2u, 0xF8u},
660                         {0xC4u, 0x71u},
661                         {0xCAu, 0x71u},
662                         {0xCCu, 0xF2u},
663                         {0xCEu, 0xFEu},
664                         {0xD6u, 0x08u},
665                         {0xD8u, 0x48u},
666                         {0xDEu, 0x80u},
667                         {0xEAu, 0x04u},
668                         {0x9Eu, 0x80u},
669                         {0xAAu, 0x40u},
670                         {0xAEu, 0xC0u},
671                         {0xB2u, 0x20u},
672                         {0xB6u, 0x10u},
673                         {0xB7u, 0x80u},
674                         {0xEAu, 0x08u},
675                         {0xEEu, 0x08u},
676                         {0x00u, 0x01u},
677                         {0x04u, 0xC4u},
678                         {0x06u, 0x12u},
679                         {0x08u, 0xF8u},
680                         {0x09u, 0x01u},
681                         {0x0Au, 0x06u},
682                         {0x0Cu, 0x40u},
683                         {0x10u, 0x04u},
684                         {0x12u, 0xAAu},
685                         {0x1Au, 0xFCu},
686                         {0x1Cu, 0x40u},
687                         {0x20u, 0x20u},
688                         {0x22u, 0x40u},
689                         {0x26u, 0x10u},
690                         {0x30u, 0x1Cu},
691                         {0x31u, 0x01u},
692                         {0x32u, 0x02u},
693                         {0x34u, 0xE0u},
694                         {0x36u, 0x01u},
695                         {0x3Eu, 0x44u},
696                         {0x3Fu, 0x01u},
697                         {0x40u, 0x46u},
698                         {0x41u, 0x02u},
699                         {0x42u, 0x30u},
700                         {0x45u, 0xD2u},
701                         {0x46u, 0xECu},
702                         {0x47u, 0x0Fu},
703                         {0x48u, 0x1Fu},
704                         {0x49u, 0xFFu},
705                         {0x4Au, 0xFFu},
706                         {0x4Bu, 0xFFu},
707                         {0x4Fu, 0x2Cu},
708                         {0x56u, 0x01u},
709                         {0x58u, 0x04u},
710                         {0x59u, 0x04u},
711                         {0x5Au, 0x04u},
712                         {0x5Bu, 0x04u},
713                         {0x5Cu, 0x09u},
714                         {0x5Du, 0x09u},
715                         {0x5Fu, 0x01u},
716                         {0x62u, 0xC0u},
717                         {0x66u, 0x80u},
718                         {0x68u, 0x40u},
719                         {0x69u, 0x40u},
720                         {0x6Eu, 0x08u},
721                         {0x8Fu, 0x02u},
722                         {0x99u, 0x03u},
723                         {0x9Bu, 0x04u},
724                         {0x9Du, 0x01u},
725                         {0xA7u, 0x07u},
726                         {0xA9u, 0x04u},
727                         {0xABu, 0x03u},
728                         {0xB3u, 0x07u},
729                         {0xD9u, 0x04u},
730                         {0xDCu, 0x90u},
731                         {0xDFu, 0x01u},
732                         {0x00u, 0x80u},
733                         {0x01u, 0x20u},
734                         {0x02u, 0x80u},
735                         {0x03u, 0x10u},
736                         {0x08u, 0x50u},
737                         {0x09u, 0x80u},
738                         {0x0Au, 0x40u},
739                         {0x12u, 0x20u},
740                         {0x13u, 0x02u},
741                         {0x19u, 0xA0u},
742                         {0x1Au, 0x54u},
743                         {0x1Bu, 0x11u},
744                         {0x22u, 0x02u},
745                         {0x27u, 0x10u},
746                         {0x2Cu, 0x10u},
747                         {0x2Du, 0x20u},
748                         {0x36u, 0x40u},
749                         {0x37u, 0x10u},
750                         {0x3Au, 0x20u},
751                         {0x3Eu, 0x40u},
752                         {0x42u, 0x50u},
753                         {0x43u, 0x10u},
754                         {0x48u, 0x40u},
755                         {0x49u, 0x21u},
756                         {0x4Au, 0x20u},
757                         {0x50u, 0x10u},
758                         {0x51u, 0x80u},
759                         {0x53u, 0x08u},
760                         {0x59u, 0x90u},
761                         {0x5Au, 0x0Au},
762                         {0x61u, 0x04u},
763                         {0x62u, 0x02u},
764                         {0x63u, 0x05u},
765                         {0x68u, 0x80u},
766                         {0x69u, 0x40u},
767                         {0x6Au, 0x20u},
768                         {0x6Bu, 0x20u},
769                         {0x70u, 0x48u},
770                         {0x72u, 0x08u},
771                         {0x73u, 0x80u},
772                         {0x78u, 0x20u},
773                         {0x7Bu, 0x08u},
774                         {0x81u, 0x40u},
775                         {0x83u, 0x02u},
776                         {0x85u, 0x20u},
777                         {0x87u, 0x20u},
778                         {0x88u, 0x10u},
779                         {0x8Du, 0x40u},
780                         {0x8Fu, 0x10u},
781                         {0x92u, 0x0Au},
782                         {0x93u, 0x05u},
783                         {0x94u, 0xA0u},
784                         {0x95u, 0x80u},
785                         {0x96u, 0x44u},
786                         {0x99u, 0x14u},
787                         {0x9Cu, 0x60u},
788                         {0x9Du, 0x01u},
789                         {0x9Eu, 0xC8u},
790                         {0x9Fu, 0x90u},
791                         {0xA2u, 0x40u},
792                         {0xA4u, 0x88u},
793                         {0xA7u, 0x91u},
794                         {0xA8u, 0x10u},
795                         {0xA9u, 0x80u},
796                         {0xAEu, 0x41u},
797                         {0xB0u, 0x48u},
798                         {0xB1u, 0x01u},
799                         {0xB2u, 0x02u},
800                         {0xB3u, 0x02u},
801                         {0xC0u, 0x0Fu},
802                         {0xC2u, 0x0Bu},
803                         {0xC4u, 0x0Cu},
804                         {0xCAu, 0x60u},
805                         {0xCCu, 0x30u},
806                         {0xCEu, 0x14u},
807                         {0xD0u, 0x07u},
808                         {0xD2u, 0x04u},
809                         {0xD6u, 0x0Fu},
810                         {0xD8u, 0x0Fu},
811                         {0xE0u, 0x20u},
812                         {0xE4u, 0x10u},
813                         {0xE6u, 0x41u},
814                         {0xE8u, 0x08u},
815                         {0x00u, 0x69u},
816                         {0x02u, 0x96u},
817                         {0x08u, 0x33u},
818                         {0x0Au, 0xCCu},
819                         {0x11u, 0x96u},
820                         {0x12u, 0xFFu},
821                         {0x13u, 0x69u},
822                         {0x17u, 0xFFu},
823                         {0x19u, 0xFFu},
824                         {0x1Au, 0xFFu},
825                         {0x1Fu, 0xFFu},
826                         {0x20u, 0x55u},
827                         {0x21u, 0x0Fu},
828                         {0x22u, 0xAAu},
829                         {0x23u, 0xF0u},
830                         {0x29u, 0x33u},
831                         {0x2Au, 0xFFu},
832                         {0x2Bu, 0xCCu},
833                         {0x2Cu, 0x0Fu},
834                         {0x2Du, 0x55u},
835                         {0x2Eu, 0xF0u},
836                         {0x2Fu, 0xAAu},
837                         {0x32u, 0xFFu},
838                         {0x35u, 0xFFu},
839                         {0x3Eu, 0x04u},
840                         {0x3Fu, 0x10u},
841                         {0x58u, 0x04u},
842                         {0x59u, 0x04u},
843                         {0x5Fu, 0x01u},
844                         {0x84u, 0x24u},
845                         {0x86u, 0x09u},
846                         {0x87u, 0x40u},
847                         {0x8Bu, 0x03u},
848                         {0x8Eu, 0x03u},
849                         {0x92u, 0x24u},
850                         {0x93u, 0x30u},
851                         {0x94u, 0x40u},
852                         {0x95u, 0x08u},
853                         {0x98u, 0x24u},
854                         {0x99u, 0x44u},
855                         {0x9Au, 0x12u},
856                         {0x9Bu, 0x11u},
857                         {0x9Eu, 0x18u},
858                         {0x9Fu, 0x04u},
859                         {0xA0u, 0x80u},
860                         {0xA5u, 0x44u},
861                         {0xA7u, 0x22u},
862                         {0xAAu, 0x04u},
863                         {0xAEu, 0x20u},
864                         {0xAFu, 0x44u},
865                         {0xB0u, 0x07u},
866                         {0xB1u, 0x70u},
867                         {0xB2u, 0x40u},
868                         {0xB3u, 0x08u},
869                         {0xB4u, 0x80u},
870                         {0xB5u, 0x07u},
871                         {0xB6u, 0x38u},
872                         {0xBEu, 0x14u},
873                         {0xBFu, 0x04u},
874                         {0xD8u, 0x04u},
875                         {0xD9u, 0x04u},
876                         {0xDBu, 0x04u},
877                         {0xDCu, 0x99u},
878                         {0xDFu, 0x01u},
879                         {0x03u, 0x12u},
880                         {0x05u, 0x22u},
881                         {0x08u, 0x04u},
882                         {0x0Au, 0x45u},
883                         {0x0Du, 0x10u},
884                         {0x0Eu, 0x80u},
885                         {0x10u, 0x08u},
886                         {0x12u, 0x40u},
887                         {0x13u, 0x80u},
888                         {0x15u, 0x80u},
889                         {0x16u, 0x82u},
890                         {0x17u, 0x20u},
891                         {0x19u, 0x14u},
892                         {0x1Au, 0x01u},
893                         {0x1Bu, 0x02u},
894                         {0x1Eu, 0x10u},
895                         {0x21u, 0x10u},
896                         {0x22u, 0x06u},
897                         {0x23u, 0x08u},
898                         {0x26u, 0x20u},
899                         {0x2Bu, 0x11u},
900                         {0x2Du, 0x20u},
901                         {0x2Eu, 0x82u},
902                         {0x30u, 0x80u},
903                         {0x31u, 0x08u},
904                         {0x32u, 0x02u},
905                         {0x33u, 0x10u},
906                         {0x35u, 0x02u},
907                         {0x36u, 0x40u},
908                         {0x37u, 0x28u},
909                         {0x39u, 0x20u},
910                         {0x3Au, 0x08u},
911                         {0x58u, 0x28u},
912                         {0x59u, 0x81u},
913                         {0x81u, 0x08u},
914                         {0x84u, 0x04u},
915                         {0x89u, 0x20u},
916                         {0x8Bu, 0x20u},
917                         {0x92u, 0x02u},
918                         {0x93u, 0x05u},
919                         {0x94u, 0x80u},
920                         {0x95u, 0x01u},
921                         {0x96u, 0x51u},
922                         {0x99u, 0x22u},
923                         {0x9Bu, 0x20u},
924                         {0x9Eu, 0x82u},
925                         {0x9Fu, 0x18u},
926                         {0xA2u, 0x40u},
927                         {0xA6u, 0x22u},
928                         {0xA7u, 0x91u},
929                         {0xB2u, 0x20u},
930                         {0xB3u, 0x01u},
931                         {0xB6u, 0x04u},
932                         {0xB7u, 0x40u},
933                         {0xC0u, 0x55u},
934                         {0xC2u, 0x5Fu},
935                         {0xC4u, 0xDBu},
936                         {0xCAu, 0xBAu},
937                         {0xCCu, 0xFFu},
938                         {0xCEu, 0x06u},
939                         {0xD6u, 0x0Fu},
940                         {0xE2u, 0x09u},
941                         {0x02u, 0x04u},
942                         {0x04u, 0x04u},
943                         {0x05u, 0x10u},
944                         {0x06u, 0x01u},
945                         {0x09u, 0x20u},
946                         {0x0Au, 0x03u},
947                         {0x0Cu, 0x80u},
948                         {0x0Fu, 0x08u},
949                         {0x11u, 0x01u},
950                         {0x12u, 0x04u},
951                         {0x14u, 0x80u},
952                         {0x17u, 0x06u},
953                         {0x18u, 0x04u},
954                         {0x19u, 0x08u},
955                         {0x1Au, 0x02u},
956                         {0x1Bu, 0x02u},
957                         {0x1Cu, 0x18u},
958                         {0x1Eu, 0x60u},
959                         {0x20u, 0x28u},
960                         {0x22u, 0x50u},
961                         {0x24u, 0x80u},
962                         {0x25u, 0x08u},
963                         {0x27u, 0x04u},
964                         {0x28u, 0x80u},
965                         {0x2Cu, 0x30u},
966                         {0x2Eu, 0x48u},
967                         {0x2Fu, 0x08u},
968                         {0x30u, 0x78u},
969                         {0x31u, 0x01u},
970                         {0x33u, 0x0Eu},
971                         {0x34u, 0x07u},
972                         {0x35u, 0x20u},
973                         {0x36u, 0x80u},
974                         {0x37u, 0x10u},
975                         {0x38u, 0x80u},
976                         {0x3Eu, 0x41u},
977                         {0x3Fu, 0x51u},
978                         {0x58u, 0x04u},
979                         {0x59u, 0x04u},
980                         {0x5Cu, 0x99u},
981                         {0x5Fu, 0x01u},
982                         {0x80u, 0x69u},
983                         {0x81u, 0x0Fu},
984                         {0x82u, 0x96u},
985                         {0x83u, 0xF0u},
986                         {0x88u, 0x33u},
987                         {0x8Au, 0xCCu},
988                         {0x8Cu, 0x0Fu},
989                         {0x8Du, 0x55u},
990                         {0x8Eu, 0xF0u},
991                         {0x8Fu, 0xAAu},
992                         {0x91u, 0x96u},
993                         {0x93u, 0x69u},
994                         {0x95u, 0xFFu},
995                         {0x9Bu, 0xFFu},
996                         {0x9Fu, 0xFFu},
997                         {0xA0u, 0x55u},
998                         {0xA2u, 0xAAu},
999                         {0xA4u, 0xFFu},
1000                         {0xA8u, 0xFFu},
1001                         {0xA9u, 0x33u},
1002                         {0xABu, 0xCCu},
1003                         {0xAEu, 0xFFu},
1004                         {0xB0u, 0xFFu},
1005                         {0xB5u, 0xFFu},
1006                         {0xBEu, 0x01u},
1007                         {0xBFu, 0x10u},
1008                         {0xD8u, 0x04u},
1009                         {0xD9u, 0x04u},
1010                         {0xDBu, 0x04u},
1011                         {0xDFu, 0x01u},
1012                         {0x01u, 0x20u},
1013                         {0x03u, 0x92u},
1014                         {0x05u, 0x22u},
1015                         {0x06u, 0x02u},
1016                         {0x08u, 0x10u},
1017                         {0x0Au, 0x51u},
1018                         {0x11u, 0x21u},
1019                         {0x12u, 0x22u},
1020                         {0x15u, 0x40u},
1021                         {0x16u, 0x80u},
1022                         {0x17u, 0x28u},
1023                         {0x19u, 0x22u},
1024                         {0x1Bu, 0x40u},
1025                         {0x1Fu, 0x02u},
1026                         {0x21u, 0x08u},
1027                         {0x22u, 0x01u},
1028                         {0x23u, 0x25u},
1029                         {0x25u, 0x10u},
1030                         {0x28u, 0x10u},
1031                         {0x2Bu, 0x11u},
1032                         {0x2Du, 0x20u},
1033                         {0x31u, 0x08u},
1034                         {0x33u, 0x11u},
1035                         {0x35u, 0x02u},
1036                         {0x36u, 0x40u},
1037                         {0x37u, 0x28u},
1038                         {0x38u, 0x80u},
1039                         {0x3Au, 0x24u},
1040                         {0x3Eu, 0x82u},
1041                         {0x6Du, 0x40u},
1042                         {0x6Eu, 0x80u},
1043                         {0x83u, 0x08u},
1044                         {0x86u, 0x02u},
1045                         {0xC0u, 0xDFu},
1046                         {0xC2u, 0x0Fu},
1047                         {0xC4u, 0xFFu},
1048                         {0xCAu, 0x2Au},
1049                         {0xCCu, 0xF7u},
1050                         {0xCEu, 0x9Eu},
1051                         {0xE0u, 0x04u},
1052                         {0xE4u, 0x08u},
1053                         {0xA8u, 0x10u},
1054                         {0xB0u, 0x01u},
1055                         {0xECu, 0x20u},
1056                         {0x82u, 0x06u},
1057                         {0x86u, 0x01u},
1058                         {0x8Au, 0x0Au},
1059                         {0x9Eu, 0x02u},
1060                         {0xA8u, 0x0Cu},
1061                         {0xAEu, 0x01u},
1062                         {0xB2u, 0x01u},
1063                         {0xB6u, 0x0Eu},
1064                         {0xBEu, 0x04u},
1065                         {0xD8u, 0x0Bu},
1066                         {0xDCu, 0x09u},
1067                         {0xDFu, 0x01u},
1068                         {0x01u, 0x20u},
1069                         {0x02u, 0x10u},
1070                         {0x03u, 0x40u},
1071                         {0x04u, 0x04u},
1072                         {0x05u, 0x20u},
1073                         {0x06u, 0x80u},
1074                         {0x0Au, 0x01u},
1075                         {0x0Du, 0x88u},
1076                         {0x12u, 0x01u},
1077                         {0x13u, 0x20u},
1078                         {0x17u, 0x60u},
1079                         {0x1Au, 0x01u},
1080                         {0x1Bu, 0x04u},
1081                         {0x1Cu, 0x04u},
1082                         {0x1Du, 0x08u},
1083                         {0x1Fu, 0x14u},
1084                         {0x24u, 0x20u},
1085                         {0x25u, 0x50u},
1086                         {0x26u, 0x10u},
1087                         {0x27u, 0x04u},
1088                         {0x2Cu, 0x80u},
1089                         {0x2Fu, 0x26u},
1090                         {0x37u, 0x64u},
1091                         {0x3Du, 0x80u},
1092                         {0x3Eu, 0x16u},
1093                         {0x44u, 0x80u},
1094                         {0x47u, 0x60u},
1095                         {0x4Cu, 0x01u},
1096                         {0x4Du, 0x20u},
1097                         {0x4Fu, 0x05u},
1098                         {0x56u, 0xA0u},
1099                         {0x57u, 0x89u},
1100                         {0x64u, 0x20u},
1101                         {0x66u, 0x20u},
1102                         {0x67u, 0x01u},
1103                         {0x7Au, 0x80u},
1104                         {0x7Eu, 0x80u},
1105                         {0x8Au, 0x01u},
1106                         {0x8Cu, 0x80u},
1107                         {0x8Du, 0x80u},
1108                         {0x90u, 0x02u},
1109                         {0x92u, 0x14u},
1110                         {0x97u, 0x24u},
1111                         {0x98u, 0x20u},
1112                         {0x99u, 0x20u},
1113                         {0x9Au, 0x13u},
1114                         {0x9Bu, 0x60u},
1115                         {0x9Cu, 0x01u},
1116                         {0x9Du, 0x80u},
1117                         {0x9Eu, 0x80u},
1118                         {0xA0u, 0x80u},
1119                         {0xA1u, 0x80u},
1120                         {0xA2u, 0x80u},
1121                         {0xA3u, 0x22u},
1122                         {0xA5u, 0x10u},
1123                         {0xA6u, 0x10u},
1124                         {0xA7u, 0x8Du},
1125                         {0xA9u, 0x08u},
1126                         {0xC0u, 0x7Eu},
1127                         {0xC2u, 0xA1u},
1128                         {0xC4u, 0xC3u},
1129                         {0xCAu, 0xF0u},
1130                         {0xCCu, 0x70u},
1131                         {0xCEu, 0xF0u},
1132                         {0xD0u, 0xB0u},
1133                         {0xD2u, 0x30u},
1134                         {0xD8u, 0x70u},
1135                         {0xDEu, 0x81u},
1136                         {0xE0u, 0x10u},
1137                         {0xE4u, 0x40u},
1138                         {0xE6u, 0x80u},
1139                         {0xE8u, 0x01u},
1140                         {0xEEu, 0x0Au},
1141                         {0xAAu, 0x80u},
1142                         {0xE8u, 0x01u},
1143                         {0xEEu, 0x0Au},
1144                         {0x0Du, 0x80u},
1145                         {0x33u, 0x80u},
1146                         {0x36u, 0x40u},
1147                         {0xC2u, 0x80u},
1148                         {0xCCu, 0x30u},
1149                         {0x53u, 0x01u},
1150                         {0x5Du, 0x20u},
1151                         {0xA1u, 0x80u},
1152                         {0xA6u, 0x40u},
1153                         {0xA7u, 0x80u},
1154                         {0xD4u, 0x80u},
1155                         {0xD6u, 0x20u},
1156                         {0x89u, 0x80u},
1157                         {0x8Fu, 0x01u},
1158                         {0x97u, 0x02u},
1159                         {0xA1u, 0x80u},
1160                         {0xA6u, 0x40u},
1161                         {0xA7u, 0x80u},
1162                         {0xADu, 0x20u},
1163                         {0xEEu, 0x40u},
1164                         {0xA6u, 0x40u},
1165                         {0xA7u, 0x80u},
1166                         {0x00u, 0x10u},
1167                         {0x09u, 0x40u},
1168                         {0x0Fu, 0x01u},
1169                         {0x11u, 0x01u},
1170                         {0x17u, 0x04u},
1171                         {0x61u, 0x20u},
1172                         {0x63u, 0x02u},
1173                         {0x81u, 0x20u},
1174                         {0x87u, 0x01u},
1175                         {0xC0u, 0x02u},
1176                         {0xC2u, 0x03u},
1177                         {0xC4u, 0x0Cu},
1178                         {0xD6u, 0x02u},
1179                         {0xD8u, 0x02u},
1180                         {0x08u, 0x04u},
1181                         {0x0Cu, 0x02u},
1182                         {0x56u, 0x20u},
1183                         {0x5Au, 0x04u},
1184                         {0x5Fu, 0x10u},
1185                         {0x62u, 0x02u},
1186                         {0x83u, 0x01u},
1187                         {0x84u, 0x02u},
1188                         {0x8Au, 0x22u},
1189                         {0x90u, 0x10u},
1190                         {0x93u, 0x01u},
1191                         {0xA0u, 0x80u},
1192                         {0xB1u, 0x41u},
1193                         {0xB4u, 0x80u},
1194                         {0xB7u, 0x04u},
1195                         {0xC2u, 0x0Cu},
1196                         {0xD4u, 0x02u},
1197                         {0xD6u, 0x06u},
1198                         {0xD8u, 0x02u},
1199                         {0xE0u, 0x04u},
1200                         {0xE4u, 0x04u},
1201                         {0xECu, 0x02u},
1202                         {0xEEu, 0x0Du},
1203                         {0x54u, 0x80u},
1204                         {0x80u, 0x10u},
1205                         {0x90u, 0x10u},
1206                         {0x98u, 0x04u},
1207                         {0xA0u, 0x80u},
1208                         {0xA2u, 0x20u},
1209                         {0xAFu, 0x10u},
1210                         {0xB2u, 0x24u},
1211                         {0xD4u, 0x02u},
1212                         {0xECu, 0x05u},
1213                         {0x08u, 0x08u},
1214                         {0x0Fu, 0x40u},
1215                         {0x9Eu, 0x02u},
1216                         {0xA2u, 0x20u},
1217                         {0xA4u, 0x10u},
1218                         {0xACu, 0x10u},
1219                         {0xAEu, 0x02u},
1220                         {0xB0u, 0x04u},
1221                         {0xC2u, 0x0Cu},
1222                         {0xEEu, 0x01u},
1223                         {0x23u, 0x20u},
1224                         {0x24u, 0x04u},
1225                         {0x8Au, 0x40u},
1226                         {0x8Cu, 0x04u},
1227                         {0x8Du, 0x04u},
1228                         {0xAEu, 0x40u},
1229                         {0xAFu, 0x80u},
1230                         {0xC8u, 0x60u},
1231                         {0xEEu, 0x50u},
1232                         {0x05u, 0x04u},
1233                         {0x51u, 0x20u},
1234                         {0x56u, 0x40u},
1235                         {0x9Au, 0x40u},
1236                         {0x9Du, 0x04u},
1237                         {0xA1u, 0x20u},
1238                         {0xA9u, 0x20u},
1239                         {0xB3u, 0x20u},
1240                         {0xC0u, 0x20u},
1241                         {0xD4u, 0x60u},
1242                         {0xEAu, 0x20u},
1243                         {0x9Bu, 0x80u},
1244                         {0x9Eu, 0x02u},
1245                         {0xA2u, 0x20u},
1246                         {0xA4u, 0x10u},
1247                         {0xABu, 0x80u},
1248                         {0xACu, 0x08u},
1249                         {0xAFu, 0x40u},
1250                         {0x00u, 0x20u},
1251                         {0x06u, 0x02u},
1252                         {0x52u, 0x20u},
1253                         {0x5Bu, 0x80u},
1254                         {0x9Bu, 0x80u},
1255                         {0x9Eu, 0x02u},
1256                         {0xA2u, 0x20u},
1257                         {0xA4u, 0x10u},
1258                         {0xC0u, 0x03u},
1259                         {0xD4u, 0x05u},
1260                         {0x01u, 0x01u},
1261                         {0x0Bu, 0x01u},
1262                         {0x0Du, 0x01u},
1263                         {0x0Fu, 0x01u},
1264                         {0x11u, 0x01u},
1265                         {0x1Bu, 0x01u},
1266                         {0x00u, 0x0Au},
1267                 };
1268
1269
1270
1271                 CYPACKED typedef struct {
1272                         void CYFAR *address;
1273                         uint16 size;
1274                 } CYPACKED_ATTR cfg_memset_t;
1275
1276
1277                 CYPACKED typedef struct {
1278                         void CYFAR *dest;
1279                         const void CYCODE *src;
1280                         uint16 size;
1281                 } CYPACKED_ATTR cfg_memcpy_t;
1282
1283                 static const cfg_memset_t CYCODE cfg_memset_list [] = {
1284                         /* address, size */
1285                         {(void CYFAR *)(CYREG_PRT1_DR), 16u},
1286                         {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
1287                         {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 512u},
1288                         {(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), 1408u},
1289                         {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
1290                         {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
1291                         {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},
1292                 };
1293
1294                 /* UDB_1_1_1_CONFIG Address: CYDEV_UCFG_B1_P3_U0_BASE Size (bytes): 128 */
1295                 static const uint8 CYCODE BS_UDB_1_1_1_CONFIG_VAL[] = {
1296                         0x00u, 0x01u, 0x02u, 0x00u, 0x40u, 0x01u, 0x30u, 0x00u, 0x34u, 0x01u, 0x43u, 0x00u, 0x00u, 0xF8u, 0x00u, 0x00u, 
1297                         0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x0Cu, 0x01u, 0x00u, 0x8Bu, 0x00u, 0x04u, 0x00u, 0x25u, 0x01u, 0x0Au, 
1298                         0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x06u, 0x00u, 0x51u, 0x58u, 0x00u, 0x23u, 0xE0u, 0x11u, 0x00u, 0x62u, 0x01u, 
1299                         0x00u, 0x00u, 0x0Fu, 0xE0u, 0x70u, 0x03u, 0x00u, 0x1Cu, 0x00u, 0x80u, 0x20u, 0x20u, 0x00u, 0x00u, 0x00u, 0x04u, 
1300                         0x62u, 0x01u, 0x50u, 0x00u, 0x04u, 0xDEu, 0xFBu, 0xCDu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, 
1301                         0x04u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x0Bu, 0x0Bu, 0x0Bu, 0x0Bu, 0x99u, 0x99u, 0x00u, 0x01u, 
1302                         0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 
1303                         0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
1304
1305                 static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
1306                         /* dest, src, size */
1307                         {(void CYFAR *)(CYDEV_UCFG_B1_P3_U0_BASE), BS_UDB_1_1_1_CONFIG_VAL, 128u},
1308                 };
1309
1310                 uint8 CYDATA i;
1311
1312                 /* Zero out critical memory blocks before beginning configuration */
1313                 for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
1314                 {
1315                         const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
1316                         CYMEMZERO(ms->address, (uint32)(ms->size));
1317                 }
1318
1319                 /* Copy device configuration data into registers */
1320                 for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)
1321                 {
1322                         const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];
1323                         void * CYDATA destPtr = mc->dest;
1324                         const void CYCODE * CYDATA srcPtr = mc->src;
1325                         uint16 CYDATA numBytes = mc->size;
1326                         CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);
1327                 }
1328
1329                 cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
1330
1331                 /* Enable digital routing */
1332                 CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);
1333                 CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);
1334
1335                 /* Enable UDB array */
1336                 CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u);
1337                 CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);
1338         }
1339
1340         /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
1341         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DR), (const void CYCODE *)(BS_IOPINS0_0_VAL), 10u);
1342         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DM0), (const void CYCODE *)(BS_IOPINS0_7_VAL), 8u);
1343         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DM0 + 0x00000009u), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u);
1344         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u);
1345         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u);
1346         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DM0), (const void CYCODE *)(BS_IOPINS0_3_VAL), 8u);
1347         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);
1348         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT5_DM0), (const void CYCODE *)(BS_IOPINS0_5_VAL), 8u);
1349         CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u);
1350
1351         /* Switch Boost to the precision bandgap reference from its internal reference */
1352         CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));
1353
1354         /* Perform basic analog initialization to defaults */
1355         AnalogSetDefault();
1356
1357         /* Configure alternate active mode */
1358         CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u);
1359 }