SWV tracing for diagnosing hangs.
[SCSI2SD.git] / software / SCSI2SD / src / scsiPhy.c
index 46852fb..8c90cb1 100755 (executable)
 //\r
 //     You should have received a copy of the GNU General Public License\r
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
+#pragma GCC push_options\r
+#pragma GCC optimize("-flto")\r
 \r
 #include "device.h"\r
 #include "scsi.h"\r
 #include "scsiPhy.h"\r
 #include "bits.h"\r
+#include "trace.h"\r
 \r
 #define scsiTarget_AUX_CTL (* (reg8 *) scsiTarget_datapath__DP_AUX_CTL_REG)\r
 \r
@@ -42,26 +45,28 @@ static uint8 scsiDmaTxTd[1] = { CY_DMA_INVALID_TD };
 // Source of dummy bytes for DMA reads\r
 static uint8 dummyBuffer = 0xFF;\r
 \r
-volatile static uint8 rxDMAComplete;\r
-volatile static uint8 txDMAComplete;\r
+volatile uint8_t scsiRxDMAComplete;\r
+volatile uint8_t scsiTxDMAComplete;\r
 \r
 CY_ISR_PROTO(scsiRxCompleteISR);\r
 CY_ISR(scsiRxCompleteISR)\r
 {\r
-       rxDMAComplete = 1;\r
+       traceIrq(trace_scsiRxCompleteISR);\r
+       scsiRxDMAComplete = 1;\r
 }\r
 \r
 CY_ISR_PROTO(scsiTxCompleteISR);\r
 CY_ISR(scsiTxCompleteISR)\r
 {\r
-       txDMAComplete = 1;\r
+       traceIrq(trace_scsiTxCompleteISR);\r
+       scsiTxDMAComplete = 1;\r
 }\r
 \r
 CY_ISR_PROTO(scsiResetISR);\r
 CY_ISR(scsiResetISR)\r
 {\r
+       traceIrq(trace_scsiResetISR);\r
        scsiDev.resetFlag = 1;\r
-       SCSI_RST_ClearInterrupt();\r
 }\r
 \r
 uint8_t\r
@@ -81,14 +86,17 @@ scsiReadDBxPins()
 uint8_t\r
 scsiReadByte(void)\r
 {\r
-       while (scsiPhyTxFifoFull() && !scsiDev.resetFlag) {}\r
+       trace(trace_spinPhyTxFifo);\r
+       while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {}\r
        scsiPhyTx(0);\r
 \r
-       while (scsiPhyRxFifoEmpty() && !scsiDev.resetFlag) {}\r
+       trace(trace_spinPhyRxFifo);\r
+       while (scsiPhyRxFifoEmpty() && likely(!scsiDev.resetFlag)) {}\r
        uint8_t val = scsiPhyRx();\r
        scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();\r
 \r
-       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}\r
+       trace(trace_spinTxComplete);\r
+       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
 \r
        return val;\r
 }\r
@@ -99,7 +107,7 @@ scsiReadPIO(uint8* data, uint32 count)
        int prep = 0;\r
        int i = 0;\r
 \r
-       while (i < count && !scsiDev.resetFlag)\r
+       while (i < count && likely(!scsiDev.resetFlag))\r
        {\r
                uint8_t status = scsiPhyStatus();\r
 \r
@@ -115,7 +123,7 @@ scsiReadPIO(uint8* data, uint32 count)
                }\r
        }\r
        scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();\r
-       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}\r
+       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
 }\r
 \r
 static void\r
@@ -123,6 +131,7 @@ doRxSingleDMA(uint8* data, uint32 count)
 {\r
        // Prepare DMA transfer\r
        dmaInProgress = 1;\r
+       trace(trace_doRxSingleDMA);\r
 \r
        CyDmaTdSetConfiguration(\r
                scsiDmaTxTd[0],\r
@@ -137,7 +146,7 @@ doRxSingleDMA(uint8* data, uint32 count)
                TD_INC_DST_ADR |\r
                        SCSI_RX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete\r
                );\r
-       \r
+\r
        CyDmaTdSetAddress(\r
                scsiDmaTxTd[0],\r
                LO16((uint32)&dummyBuffer),\r
@@ -147,18 +156,18 @@ doRxSingleDMA(uint8* data, uint32 count)
                LO16((uint32)scsiTarget_datapath__F1_REG),\r
                LO16((uint32)data)\r
                );\r
-       \r
+\r
        CyDmaChSetInitialTd(scsiDmaTxChan, scsiDmaTxTd[0]);\r
        CyDmaChSetInitialTd(scsiDmaRxChan, scsiDmaRxTd[0]);\r
-       \r
+\r
        // The DMA controller is a bit trigger-happy. It will retain\r
        // a drq request that was triggered while the channel was\r
        // disabled.\r
        CyDmaClearPendingDrq(scsiDmaTxChan);\r
        CyDmaClearPendingDrq(scsiDmaRxChan);\r
 \r
-       txDMAComplete = 0;\r
-       rxDMAComplete = 0;\r
+       scsiTxDMAComplete = 0;\r
+       scsiRxDMAComplete = 0;\r
 \r
        CyDmaChEnable(scsiDmaRxChan, 1);\r
        CyDmaChEnable(scsiDmaTxChan, 1);\r
@@ -179,9 +188,14 @@ scsiReadDMA(uint8* data, uint32 count)
 int\r
 scsiReadDMAPoll()\r
 {\r
-       if (txDMAComplete && rxDMAComplete && (scsiPhyStatus() & SCSI_PHY_TX_COMPLETE))\r
+       if (scsiTxDMAComplete && scsiRxDMAComplete)\r
        {\r
-               if (dmaSentCount == dmaTotalCount)\r
+               // Wait until our scsi signals are consistent. This should only be\r
+               // a few cycles.\r
+               trace(trace_spinTxComplete);\r
+               while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {}\r
+\r
+               if (likely(dmaSentCount == dmaTotalCount))\r
                {\r
                        dmaInProgress = 0;\r
                        scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();\r
@@ -192,7 +206,7 @@ scsiReadDMAPoll()
                        // Transfer was too large for a single DMA transfer. Continue\r
                        // to send remaining bytes.\r
                        uint32_t count = dmaTotalCount - dmaSentCount;\r
-                       if (count > MAX_DMA_BYTES) count = MAX_DMA_BYTES;\r
+                       if (unlikely(count > MAX_DMA_BYTES)) count = MAX_DMA_BYTES;\r
                        doRxSingleDMA(dmaBuffer + dmaSentCount, count);\r
                        dmaSentCount += count;\r
                        return 0;\r
@@ -214,26 +228,35 @@ scsiRead(uint8_t* data, uint32_t count)
        else\r
        {\r
                scsiReadDMA(data, count);\r
-               while (!scsiReadDMAPoll() && !scsiDev.resetFlag) {};\r
+\r
+               // Wait for the next DMA interrupt (or the 1ms systick)\r
+               // It's beneficial to halt the processor to\r
+               // give the DMA controller more memory bandwidth to work with.\r
+               __WFI();\r
+\r
+               trace(trace_spinReadDMAPoll);\r
+               while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag)) {};\r
        }\r
 }\r
 \r
 void\r
 scsiWriteByte(uint8 value)\r
 {\r
-       while (scsiPhyTxFifoFull() && !scsiDev.resetFlag) {}\r
+       trace(trace_spinPhyTxFifo);\r
+       while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {}\r
        scsiPhyTx(value);\r
 \r
-       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}\r
+       trace(trace_spinTxComplete);\r
+       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
        scsiPhyRxFifoClear();\r
 }\r
 \r
 static void\r
-scsiWritePIO(uint8_t* data, uint32_t count)\r
+scsiWritePIO(const uint8_t* data, uint32_t count)\r
 {\r
        int i = 0;\r
 \r
-       while (i < count && !scsiDev.resetFlag)\r
+       while (i < count && likely(!scsiDev.resetFlag))\r
        {\r
                if (!scsiPhyTxFifoFull())\r
                {\r
@@ -242,15 +265,17 @@ scsiWritePIO(uint8_t* data, uint32_t count)
                }\r
        }\r
 \r
-       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}\r
+       trace(trace_spinTxComplete);\r
+       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
        scsiPhyRxFifoClear();\r
 }\r
 \r
 static void\r
-doTxSingleDMA(uint8* data, uint32 count)\r
+doTxSingleDMA(const uint8* data, uint32 count)\r
 {\r
        // Prepare DMA transfer\r
        dmaInProgress = 1;\r
+       trace(trace_doTxSingleDMA);\r
 \r
        CyDmaTdSetConfiguration(\r
                scsiDmaTxTd[0],\r
@@ -270,14 +295,14 @@ doTxSingleDMA(uint8* data, uint32 count)
        // disabled.\r
        CyDmaClearPendingDrq(scsiDmaTxChan);\r
 \r
-       txDMAComplete = 0;\r
-       rxDMAComplete = 1;\r
+       scsiTxDMAComplete = 0;\r
+       scsiRxDMAComplete = 1;\r
 \r
        CyDmaChEnable(scsiDmaTxChan, 1);\r
 }\r
 \r
 void\r
-scsiWriteDMA(uint8* data, uint32 count)\r
+scsiWriteDMA(const uint8* data, uint32 count)\r
 {\r
        dmaSentCount = 0;\r
        dmaTotalCount = count;\r
@@ -291,9 +316,14 @@ scsiWriteDMA(uint8* data, uint32 count)
 int\r
 scsiWriteDMAPoll()\r
 {\r
-       if (txDMAComplete && (scsiPhyStatus() & SCSI_PHY_TX_COMPLETE))\r
+       if (scsiTxDMAComplete)\r
        {\r
-               if (dmaSentCount == dmaTotalCount)\r
+               // Wait until our scsi signals are consistent. This should only be\r
+               // a few cycles.\r
+               trace(trace_spinTxComplete);\r
+               while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {}\r
+\r
+               if (likely(dmaSentCount == dmaTotalCount))\r
                {\r
                        scsiPhyRxFifoClear();\r
                        dmaInProgress = 0;\r
@@ -304,7 +334,7 @@ scsiWriteDMAPoll()
                        // Transfer was too large for a single DMA transfer. Continue\r
                        // to send remaining bytes.\r
                        uint32_t count = dmaTotalCount - dmaSentCount;\r
-                       if (count > MAX_DMA_BYTES) count = MAX_DMA_BYTES;\r
+                       if (unlikely(count > MAX_DMA_BYTES)) count = MAX_DMA_BYTES;\r
                        doTxSingleDMA(dmaBuffer + dmaSentCount, count);\r
                        dmaSentCount += count;\r
                        return 0;\r
@@ -317,7 +347,7 @@ scsiWriteDMAPoll()
 }\r
 \r
 void\r
-scsiWrite(uint8_t* data, uint32_t count)\r
+scsiWrite(const uint8_t* data, uint32_t count)\r
 {\r
        if (count < 8)\r
        {\r
@@ -326,11 +356,18 @@ scsiWrite(uint8_t* data, uint32_t count)
        else\r
        {\r
                scsiWriteDMA(data, count);\r
-               while (!scsiWriteDMAPoll() && !scsiDev.resetFlag) {};\r
+\r
+               // Wait for the next DMA interrupt (or the 1ms systick)\r
+               // It's beneficial to halt the processor to\r
+               // give the DMA controller more memory bandwidth to work with.\r
+               __WFI();\r
+\r
+               trace(trace_spinWriteDMAPoll);\r
+               while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag)) {};\r
        }\r
 }\r
 \r
-static void busSettleDelay(void)\r
+static inline void busSettleDelay(void)\r
 {\r
        // Data Release time (switching IO) = 400ns\r
        // + Bus Settle time (switching phase) = 400ns.\r
@@ -349,6 +386,7 @@ void scsiEnterPhase(int phase)
 \r
 void scsiPhyReset()\r
 {\r
+       trace(trace_scsiPhyReset);\r
        if (dmaInProgress)\r
        {\r
                dmaInProgress = 0;\r
@@ -357,7 +395,8 @@ void scsiPhyReset()
                dmaTotalCount = 0;\r
                CyDmaChSetRequest(scsiDmaTxChan, CY_DMA_CPU_TERM_CHAIN);\r
                CyDmaChSetRequest(scsiDmaRxChan, CY_DMA_CPU_TERM_CHAIN);\r
-               while (!(txDMAComplete && rxDMAComplete)) {}\r
+               trace(trace_spinDMAReset);\r
+               while (!(scsiTxDMAComplete && scsiRxDMAComplete)) {}\r
 \r
                CyDmaChDisable(scsiDmaTxChan);\r
                CyDmaChDisable(scsiDmaRxChan);\r
@@ -407,7 +446,7 @@ static void scsiPhyInitDMA()
                                HI16(CYDEV_SRAM_BASE),\r
                                HI16(CYDEV_PERIPH_BASE)\r
                                );\r
-\r
+               \r
                CyDmaChDisable(scsiDmaRxChan);\r
                CyDmaChDisable(scsiDmaTxChan);\r
 \r
@@ -425,8 +464,88 @@ void scsiPhyInit()
        scsiPhyInitDMA();\r
 \r
        SCSI_RST_ISR_StartEx(scsiResetISR);\r
+}\r
+\r
+// 1 = DBx error\r
+// 2 = Parity error\r
+// 4 = MSG error\r
+// 8 = CD error\r
+// 16 = IO error\r
+// 32 = other error\r
+int scsiSelfTest()\r
+{\r
+       int result = 0;\r
+\r
+       // TEST DBx and DBp\r
+       int i;\r
+       SCSI_Out_Ctl_Write(1); // Write bits manually.\r
+       SCSI_CTL_PHASE_Write(__scsiphase_io); // Needed for parity generation\r
+       for (i = 0; i < 256; ++i)\r
+       {\r
+               SCSI_Out_Bits_Write(i);\r
+               scsiDeskewDelay();\r
+               if (scsiReadDBxPins() != (i & 0xff))\r
+               {\r
+                       result |= 1;\r
+               }\r
+               if (Lookup_OddParity[i & 0xff] != SCSI_ReadPin(SCSI_In_DBP))\r
+               {\r
+                       result |= 2;\r
+               }\r
+       }\r
+       SCSI_Out_Ctl_Write(0); // Write bits normally.\r
 \r
-       // Interrupts may have already been directed to the (empty)\r
-       // standard ISR generated by PSoC Creator.\r
-       SCSI_RST_ClearInterrupt();\r
+       // TEST MSG, CD, IO\r
+       for (i = 0; i < 8; ++i)\r
+       {\r
+               SCSI_CTL_PHASE_Write(i);\r
+               scsiDeskewDelay();\r
+\r
+               if (SCSI_ReadPin(SCSI_In_MSG) != !!(i & __scsiphase_msg))\r
+               {\r
+                       result |= 4;\r
+               }\r
+               if (SCSI_ReadPin(SCSI_In_CD) != !!(i & __scsiphase_cd))\r
+               {\r
+                       result |= 8;\r
+               }\r
+               if (SCSI_ReadPin(SCSI_In_IO) != !!(i & __scsiphase_io))\r
+               {\r
+                       result |= 16;\r
+               }\r
+       }\r
+       SCSI_CTL_PHASE_Write(0);\r
+\r
+       uint32_t signalsOut[] = { SCSI_Out_ATN, SCSI_Out_BSY, SCSI_Out_RST, SCSI_Out_SEL };\r
+       uint32_t signalsIn[] = { SCSI_Filt_ATN, SCSI_Filt_BSY, SCSI_Filt_RST, SCSI_Filt_SEL };\r
+\r
+       for (i = 0; i < 4; ++i)\r
+       {\r
+               SCSI_SetPin(signalsOut[i]);\r
+               scsiDeskewDelay();\r
+\r
+               int j;\r
+               for (j = 0; j < 4; ++j)\r
+               {\r
+                       if (i == j)\r
+                       {\r
+                               if (! SCSI_ReadFilt(signalsIn[j]))\r
+                               {\r
+                                       result |= 32;\r
+                               }\r
+                       }\r
+                       else\r
+                       {\r
+                               if (SCSI_ReadFilt(signalsIn[j]))\r
+                               {\r
+                                       result |= 32;\r
+                               }\r
+                       }\r
+               }\r
+               SCSI_ClearPin(signalsOut[i]);\r
+       }\r
+       return result;\r
 }\r
+\r
+\r
+#pragma GCC pop_options\r