SWV tracing for diagnosing hangs.
[SCSI2SD.git] / software / SCSI2SD / src / scsiPhy.c
index 5952b85..8c90cb1 100755 (executable)
@@ -21,6 +21,7 @@
 #include "scsi.h"\r
 #include "scsiPhy.h"\r
 #include "bits.h"\r
+#include "trace.h"\r
 \r
 #define scsiTarget_AUX_CTL (* (reg8 *) scsiTarget_datapath__DP_AUX_CTL_REG)\r
 \r
@@ -50,18 +51,21 @@ volatile uint8_t scsiTxDMAComplete;
 CY_ISR_PROTO(scsiRxCompleteISR);\r
 CY_ISR(scsiRxCompleteISR)\r
 {\r
+       traceIrq(trace_scsiRxCompleteISR);\r
        scsiRxDMAComplete = 1;\r
 }\r
 \r
 CY_ISR_PROTO(scsiTxCompleteISR);\r
 CY_ISR(scsiTxCompleteISR)\r
 {\r
+       traceIrq(trace_scsiTxCompleteISR);\r
        scsiTxDMAComplete = 1;\r
 }\r
 \r
 CY_ISR_PROTO(scsiResetISR);\r
 CY_ISR(scsiResetISR)\r
 {\r
+       traceIrq(trace_scsiResetISR);\r
        scsiDev.resetFlag = 1;\r
 }\r
 \r
@@ -82,13 +86,16 @@ scsiReadDBxPins()
 uint8_t\r
 scsiReadByte(void)\r
 {\r
+       trace(trace_spinPhyTxFifo);\r
        while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {}\r
        scsiPhyTx(0);\r
 \r
+       trace(trace_spinPhyRxFifo);\r
        while (scsiPhyRxFifoEmpty() && likely(!scsiDev.resetFlag)) {}\r
        uint8_t val = scsiPhyRx();\r
        scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();\r
 \r
+       trace(trace_spinTxComplete);\r
        while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
 \r
        return val;\r
@@ -124,6 +131,7 @@ doRxSingleDMA(uint8* data, uint32 count)
 {\r
        // Prepare DMA transfer\r
        dmaInProgress = 1;\r
+       trace(trace_doRxSingleDMA);\r
 \r
        CyDmaTdSetConfiguration(\r
                scsiDmaTxTd[0],\r
@@ -184,6 +192,7 @@ scsiReadDMAPoll()
        {\r
                // Wait until our scsi signals are consistent. This should only be\r
                // a few cycles.\r
+               trace(trace_spinTxComplete);\r
                while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {}\r
 \r
                if (likely(dmaSentCount == dmaTotalCount))\r
@@ -219,12 +228,13 @@ scsiRead(uint8_t* data, uint32_t count)
        else\r
        {\r
                scsiReadDMA(data, count);\r
-               \r
+\r
                // Wait for the next DMA interrupt (or the 1ms systick)\r
                // It's beneficial to halt the processor to\r
                // give the DMA controller more memory bandwidth to work with.\r
                __WFI();\r
-               \r
+\r
+               trace(trace_spinReadDMAPoll);\r
                while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag)) {};\r
        }\r
 }\r
@@ -232,9 +242,11 @@ scsiRead(uint8_t* data, uint32_t count)
 void\r
 scsiWriteByte(uint8 value)\r
 {\r
+       trace(trace_spinPhyTxFifo);\r
        while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {}\r
        scsiPhyTx(value);\r
 \r
+       trace(trace_spinTxComplete);\r
        while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
        scsiPhyRxFifoClear();\r
 }\r
@@ -253,6 +265,7 @@ scsiWritePIO(const uint8_t* data, uint32_t count)
                }\r
        }\r
 \r
+       trace(trace_spinTxComplete);\r
        while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
        scsiPhyRxFifoClear();\r
 }\r
@@ -262,6 +275,7 @@ doTxSingleDMA(const uint8* data, uint32 count)
 {\r
        // Prepare DMA transfer\r
        dmaInProgress = 1;\r
+       trace(trace_doTxSingleDMA);\r
 \r
        CyDmaTdSetConfiguration(\r
                scsiDmaTxTd[0],\r
@@ -306,6 +320,7 @@ scsiWriteDMAPoll()
        {\r
                // Wait until our scsi signals are consistent. This should only be\r
                // a few cycles.\r
+               trace(trace_spinTxComplete);\r
                while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {}\r
 \r
                if (likely(dmaSentCount == dmaTotalCount))\r
@@ -341,12 +356,13 @@ scsiWrite(const uint8_t* data, uint32_t count)
        else\r
        {\r
                scsiWriteDMA(data, count);\r
-               \r
+\r
                // Wait for the next DMA interrupt (or the 1ms systick)\r
                // It's beneficial to halt the processor to\r
                // give the DMA controller more memory bandwidth to work with.\r
                __WFI();\r
 \r
+               trace(trace_spinWriteDMAPoll);\r
                while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag)) {};\r
        }\r
 }\r
@@ -370,6 +386,7 @@ void scsiEnterPhase(int phase)
 \r
 void scsiPhyReset()\r
 {\r
+       trace(trace_scsiPhyReset);\r
        if (dmaInProgress)\r
        {\r
                dmaInProgress = 0;\r
@@ -378,6 +395,7 @@ void scsiPhyReset()
                dmaTotalCount = 0;\r
                CyDmaChSetRequest(scsiDmaTxChan, CY_DMA_CPU_TERM_CHAIN);\r
                CyDmaChSetRequest(scsiDmaRxChan, CY_DMA_CPU_TERM_CHAIN);\r
+               trace(trace_spinDMAReset);\r
                while (!(scsiTxDMAComplete && scsiRxDMAComplete)) {}\r
 \r
                CyDmaChDisable(scsiDmaTxChan);\r
@@ -447,4 +465,87 @@ void scsiPhyInit()
 \r
        SCSI_RST_ISR_StartEx(scsiResetISR);\r
 }\r
+\r
+// 1 = DBx error\r
+// 2 = Parity error\r
+// 4 = MSG error\r
+// 8 = CD error\r
+// 16 = IO error\r
+// 32 = other error\r
+int scsiSelfTest()\r
+{\r
+       int result = 0;\r
+\r
+       // TEST DBx and DBp\r
+       int i;\r
+       SCSI_Out_Ctl_Write(1); // Write bits manually.\r
+       SCSI_CTL_PHASE_Write(__scsiphase_io); // Needed for parity generation\r
+       for (i = 0; i < 256; ++i)\r
+       {\r
+               SCSI_Out_Bits_Write(i);\r
+               scsiDeskewDelay();\r
+               if (scsiReadDBxPins() != (i & 0xff))\r
+               {\r
+                       result |= 1;\r
+               }\r
+               if (Lookup_OddParity[i & 0xff] != SCSI_ReadPin(SCSI_In_DBP))\r
+               {\r
+                       result |= 2;\r
+               }\r
+       }\r
+       SCSI_Out_Ctl_Write(0); // Write bits normally.\r
+\r
+       // TEST MSG, CD, IO\r
+       for (i = 0; i < 8; ++i)\r
+       {\r
+               SCSI_CTL_PHASE_Write(i);\r
+               scsiDeskewDelay();\r
+\r
+               if (SCSI_ReadPin(SCSI_In_MSG) != !!(i & __scsiphase_msg))\r
+               {\r
+                       result |= 4;\r
+               }\r
+               if (SCSI_ReadPin(SCSI_In_CD) != !!(i & __scsiphase_cd))\r
+               {\r
+                       result |= 8;\r
+               }\r
+               if (SCSI_ReadPin(SCSI_In_IO) != !!(i & __scsiphase_io))\r
+               {\r
+                       result |= 16;\r
+               }\r
+       }\r
+       SCSI_CTL_PHASE_Write(0);\r
+\r
+       uint32_t signalsOut[] = { SCSI_Out_ATN, SCSI_Out_BSY, SCSI_Out_RST, SCSI_Out_SEL };\r
+       uint32_t signalsIn[] = { SCSI_Filt_ATN, SCSI_Filt_BSY, SCSI_Filt_RST, SCSI_Filt_SEL };\r
+\r
+       for (i = 0; i < 4; ++i)\r
+       {\r
+               SCSI_SetPin(signalsOut[i]);\r
+               scsiDeskewDelay();\r
+\r
+               int j;\r
+               for (j = 0; j < 4; ++j)\r
+               {\r
+                       if (i == j)\r
+                       {\r
+                               if (! SCSI_ReadFilt(signalsIn[j]))\r
+                               {\r
+                                       result |= 32;\r
+                               }\r
+                       }\r
+                       else\r
+                       {\r
+                               if (SCSI_ReadFilt(signalsIn[j]))\r
+                               {\r
+                                       result |= 32;\r
+                               }\r
+                       }\r
+               }\r
+               SCSI_ClearPin(signalsOut[i]);\r
+       }\r
+       return result;\r
+}\r
+\r
+\r
 #pragma GCC pop_options\r