SWV tracing for diagnosing hangs.
[SCSI2SD.git] / software / SCSI2SD / src / scsiPhy.c
index fc42b4f..8c90cb1 100755 (executable)
 //\r
 //     You should have received a copy of the GNU General Public License\r
 //     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.\r
+#pragma GCC push_options\r
+#pragma GCC optimize("-flto")\r
 \r
 #include "device.h"\r
 #include "scsi.h"\r
 #include "scsiPhy.h"\r
 #include "bits.h"\r
+#include "trace.h"\r
 \r
 #define scsiTarget_AUX_CTL (* (reg8 *) scsiTarget_datapath__DP_AUX_CTL_REG)\r
 \r
+// DMA controller can't handle any more bytes.\r
+#define MAX_DMA_BYTES 4095\r
+\r
+// Private DMA variables.\r
+static int dmaInProgress = 0;\r
+// used when transferring > MAX_DMA_BYTES.\r
+static uint8_t* dmaBuffer = NULL;\r
+static uint32_t dmaSentCount = 0;\r
+static uint32_t dmaTotalCount = 0;\r
+\r
+static uint8 scsiDmaRxChan = CY_DMA_INVALID_CHANNEL;\r
+static uint8 scsiDmaTxChan = CY_DMA_INVALID_CHANNEL;\r
+\r
+// DMA descriptors\r
+static uint8 scsiDmaRxTd[1] = { CY_DMA_INVALID_TD };\r
+static uint8 scsiDmaTxTd[1] = { CY_DMA_INVALID_TD };\r
+\r
+// Source of dummy bytes for DMA reads\r
+static uint8 dummyBuffer = 0xFF;\r
+\r
+volatile uint8_t scsiRxDMAComplete;\r
+volatile uint8_t scsiTxDMAComplete;\r
+\r
+CY_ISR_PROTO(scsiRxCompleteISR);\r
+CY_ISR(scsiRxCompleteISR)\r
+{\r
+       traceIrq(trace_scsiRxCompleteISR);\r
+       scsiRxDMAComplete = 1;\r
+}\r
+\r
+CY_ISR_PROTO(scsiTxCompleteISR);\r
+CY_ISR(scsiTxCompleteISR)\r
+{\r
+       traceIrq(trace_scsiTxCompleteISR);\r
+       scsiTxDMAComplete = 1;\r
+}\r
+\r
 CY_ISR_PROTO(scsiResetISR);\r
 CY_ISR(scsiResetISR)\r
 {\r
+       traceIrq(trace_scsiResetISR);\r
        scsiDev.resetFlag = 1;\r
-       SCSI_RST_ClearInterrupt();\r
 }\r
 \r
-uint8 scsiReadDBxPins()\r
+uint8_t\r
+scsiReadDBxPins()\r
 {\r
        return\r
                (SCSI_ReadPin(SCSI_In_DBx_DB7) << 7) |\r
@@ -39,82 +80,294 @@ uint8 scsiReadDBxPins()
                (SCSI_ReadPin(SCSI_In_DBx_DB3) << 3) |\r
                (SCSI_ReadPin(SCSI_In_DBx_DB2) << 2) |\r
                (SCSI_ReadPin(SCSI_In_DBx_DB1) << 1) |\r
-               SCSI_ReadPin(SCSI_In_DBx_DB0);          \r
+               SCSI_ReadPin(SCSI_In_DBx_DB0);\r
 }\r
 \r
-uint8 scsiReadByte(void)\r
+uint8_t\r
+scsiReadByte(void)\r
 {\r
-       while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1) &&\r
-               !scsiDev.resetFlag) {}\r
-       CY_SET_REG8(scsiTarget_datapath__F0_REG, 0);\r
-       while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2) &&\r
-               !scsiDev.resetFlag) {}\r
-               \r
-       while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
-               \r
-       return CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
+       trace(trace_spinPhyTxFifo);\r
+       while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {}\r
+       scsiPhyTx(0);\r
+\r
+       trace(trace_spinPhyRxFifo);\r
+       while (scsiPhyRxFifoEmpty() && likely(!scsiDev.resetFlag)) {}\r
+       uint8_t val = scsiPhyRx();\r
+       scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();\r
+\r
+       trace(trace_spinTxComplete);\r
+       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
+\r
+       return val;\r
 }\r
 \r
-void scsiRead(uint8* data, uint32 count)\r
+static void\r
+scsiReadPIO(uint8* data, uint32 count)\r
 {\r
        int prep = 0;\r
        int i = 0;\r
 \r
-       while (i < count && !scsiDev.resetFlag)\r
+       while (i < count && likely(!scsiDev.resetFlag))\r
        {\r
-               if (prep < count && (CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1))\r
+               uint8_t status = scsiPhyStatus();\r
+\r
+               if (prep < count && (status & SCSI_PHY_TX_FIFO_NOT_FULL))\r
                {\r
-                       CY_SET_REG8(scsiTarget_datapath__F0_REG, 0);\r
+                       scsiPhyTx(0);\r
                        ++prep;\r
                }\r
-               if ((CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2))\r
+               if (status & SCSI_PHY_RX_FIFO_NOT_EMPTY)\r
                {\r
-                       data[i] =  CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
+                       data[i] = scsiPhyRx();\r
                        ++i;\r
                }\r
        }\r
-       while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
+       scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();\r
+       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
+}\r
+\r
+static void\r
+doRxSingleDMA(uint8* data, uint32 count)\r
+{\r
+       // Prepare DMA transfer\r
+       dmaInProgress = 1;\r
+       trace(trace_doRxSingleDMA);\r
+\r
+       CyDmaTdSetConfiguration(\r
+               scsiDmaTxTd[0],\r
+               count,\r
+               CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes\r
+               SCSI_TX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete\r
+               );\r
+       CyDmaTdSetConfiguration(\r
+               scsiDmaRxTd[0],\r
+               count,\r
+               CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes\r
+               TD_INC_DST_ADR |\r
+                       SCSI_RX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete\r
+               );\r
+\r
+       CyDmaTdSetAddress(\r
+               scsiDmaTxTd[0],\r
+               LO16((uint32)&dummyBuffer),\r
+               LO16((uint32)scsiTarget_datapath__F0_REG));\r
+       CyDmaTdSetAddress(\r
+               scsiDmaRxTd[0],\r
+               LO16((uint32)scsiTarget_datapath__F1_REG),\r
+               LO16((uint32)data)\r
+               );\r
+\r
+       CyDmaChSetInitialTd(scsiDmaTxChan, scsiDmaTxTd[0]);\r
+       CyDmaChSetInitialTd(scsiDmaRxChan, scsiDmaRxTd[0]);\r
+\r
+       // The DMA controller is a bit trigger-happy. It will retain\r
+       // a drq request that was triggered while the channel was\r
+       // disabled.\r
+       CyDmaClearPendingDrq(scsiDmaTxChan);\r
+       CyDmaClearPendingDrq(scsiDmaRxChan);\r
 \r
+       scsiTxDMAComplete = 0;\r
+       scsiRxDMAComplete = 0;\r
+\r
+       CyDmaChEnable(scsiDmaRxChan, 1);\r
+       CyDmaChEnable(scsiDmaTxChan, 1);\r
 }\r
 \r
-void scsiWriteByte(uint8 value)\r
+void\r
+scsiReadDMA(uint8* data, uint32 count)\r
 {\r
-       while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1) &&\r
-               !scsiDev.resetFlag) {}\r
-       CY_SET_REG8(scsiTarget_datapath__F0_REG, value);\r
+       dmaSentCount = 0;\r
+       dmaTotalCount = count;\r
+       dmaBuffer = data;\r
 \r
-       // TODO maybe move this TX EMPTY check to scsiEnterPhase ?\r
-       //while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 4)) {}\r
-       while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2) &&\r
-               !scsiDev.resetFlag) {}\r
-       value = CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
-       \r
-       while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
+       uint32_t singleCount = (count > MAX_DMA_BYTES) ? MAX_DMA_BYTES : count;\r
+       doRxSingleDMA(data, singleCount);\r
+       dmaSentCount += count;\r
 }\r
 \r
-void scsiWrite(uint8* data, uint32 count)\r
+int\r
+scsiReadDMAPoll()\r
+{\r
+       if (scsiTxDMAComplete && scsiRxDMAComplete)\r
+       {\r
+               // Wait until our scsi signals are consistent. This should only be\r
+               // a few cycles.\r
+               trace(trace_spinTxComplete);\r
+               while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {}\r
+\r
+               if (likely(dmaSentCount == dmaTotalCount))\r
+               {\r
+                       dmaInProgress = 0;\r
+                       scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();\r
+                       return 1;\r
+               }\r
+               else\r
+               {\r
+                       // Transfer was too large for a single DMA transfer. Continue\r
+                       // to send remaining bytes.\r
+                       uint32_t count = dmaTotalCount - dmaSentCount;\r
+                       if (unlikely(count > MAX_DMA_BYTES)) count = MAX_DMA_BYTES;\r
+                       doRxSingleDMA(dmaBuffer + dmaSentCount, count);\r
+                       dmaSentCount += count;\r
+                       return 0;\r
+               }\r
+       }\r
+       else\r
+       {\r
+               return 0;\r
+       }\r
+}\r
+\r
+void\r
+scsiRead(uint8_t* data, uint32_t count)\r
+{\r
+       if (count < 8)\r
+       {\r
+               scsiReadPIO(data, count);\r
+       }\r
+       else\r
+       {\r
+               scsiReadDMA(data, count);\r
+\r
+               // Wait for the next DMA interrupt (or the 1ms systick)\r
+               // It's beneficial to halt the processor to\r
+               // give the DMA controller more memory bandwidth to work with.\r
+               __WFI();\r
+\r
+               trace(trace_spinReadDMAPoll);\r
+               while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag)) {};\r
+       }\r
+}\r
+\r
+void\r
+scsiWriteByte(uint8 value)\r
+{\r
+       trace(trace_spinPhyTxFifo);\r
+       while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {}\r
+       scsiPhyTx(value);\r
+\r
+       trace(trace_spinTxComplete);\r
+       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
+       scsiPhyRxFifoClear();\r
+}\r
+\r
+static void\r
+scsiWritePIO(const uint8_t* data, uint32_t count)\r
 {\r
-       int prep = 0;\r
        int i = 0;\r
 \r
-       while (i < count && !scsiDev.resetFlag)\r
+       while (i < count && likely(!scsiDev.resetFlag))\r
        {\r
-               if (prep < count && (CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1))\r
+               if (!scsiPhyTxFifoFull())\r
                {\r
-                       CY_SET_REG8(scsiTarget_datapath__F0_REG, data[prep]);\r
-                       ++prep;\r
+                       scsiPhyTx(data[i]);\r
+                       ++i;\r
                }\r
-               if ((CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2))\r
+       }\r
+\r
+       trace(trace_spinTxComplete);\r
+       while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}\r
+       scsiPhyRxFifoClear();\r
+}\r
+\r
+static void\r
+doTxSingleDMA(const uint8* data, uint32 count)\r
+{\r
+       // Prepare DMA transfer\r
+       dmaInProgress = 1;\r
+       trace(trace_doTxSingleDMA);\r
+\r
+       CyDmaTdSetConfiguration(\r
+               scsiDmaTxTd[0],\r
+               count,\r
+               CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes\r
+               TD_INC_SRC_ADR |\r
+                       SCSI_TX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete\r
+               );\r
+       CyDmaTdSetAddress(\r
+               scsiDmaTxTd[0],\r
+               LO16((uint32)data),\r
+               LO16((uint32)scsiTarget_datapath__F0_REG));\r
+       CyDmaChSetInitialTd(scsiDmaTxChan, scsiDmaTxTd[0]);\r
+\r
+       // The DMA controller is a bit trigger-happy. It will retain\r
+       // a drq request that was triggered while the channel was\r
+       // disabled.\r
+       CyDmaClearPendingDrq(scsiDmaTxChan);\r
+\r
+       scsiTxDMAComplete = 0;\r
+       scsiRxDMAComplete = 1;\r
+\r
+       CyDmaChEnable(scsiDmaTxChan, 1);\r
+}\r
+\r
+void\r
+scsiWriteDMA(const uint8* data, uint32 count)\r
+{\r
+       dmaSentCount = 0;\r
+       dmaTotalCount = count;\r
+       dmaBuffer = data;\r
+\r
+       uint32_t singleCount = (count > MAX_DMA_BYTES) ? MAX_DMA_BYTES : count;\r
+       doTxSingleDMA(data, singleCount);\r
+       dmaSentCount += count;\r
+}\r
+\r
+int\r
+scsiWriteDMAPoll()\r
+{\r
+       if (scsiTxDMAComplete)\r
+       {\r
+               // Wait until our scsi signals are consistent. This should only be\r
+               // a few cycles.\r
+               trace(trace_spinTxComplete);\r
+               while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {}\r
+\r
+               if (likely(dmaSentCount == dmaTotalCount))\r
                {\r
-                       CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
-                       ++i;\r
+                       scsiPhyRxFifoClear();\r
+                       dmaInProgress = 0;\r
+                       return 1;\r
+               }\r
+               else\r
+               {\r
+                       // Transfer was too large for a single DMA transfer. Continue\r
+                       // to send remaining bytes.\r
+                       uint32_t count = dmaTotalCount - dmaSentCount;\r
+                       if (unlikely(count > MAX_DMA_BYTES)) count = MAX_DMA_BYTES;\r
+                       doTxSingleDMA(dmaBuffer + dmaSentCount, count);\r
+                       dmaSentCount += count;\r
+                       return 0;\r
                }\r
        }\r
-       \r
-       while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
+       else\r
+       {\r
+               return 0;\r
+       }\r
 }\r
 \r
-static void busSettleDelay(void)\r
+void\r
+scsiWrite(const uint8_t* data, uint32_t count)\r
+{\r
+       if (count < 8)\r
+       {\r
+               scsiWritePIO(data, count);\r
+       }\r
+       else\r
+       {\r
+               scsiWriteDMA(data, count);\r
+\r
+               // Wait for the next DMA interrupt (or the 1ms systick)\r
+               // It's beneficial to halt the processor to\r
+               // give the DMA controller more memory bandwidth to work with.\r
+               __WFI();\r
+\r
+               trace(trace_spinWriteDMAPoll);\r
+               while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag)) {};\r
+       }\r
+}\r
+\r
+static inline void busSettleDelay(void)\r
 {\r
        // Data Release time (switching IO) = 400ns\r
        // + Bus Settle time (switching phase) = 400ns.\r
@@ -133,6 +386,22 @@ void scsiEnterPhase(int phase)
 \r
 void scsiPhyReset()\r
 {\r
+       trace(trace_scsiPhyReset);\r
+       if (dmaInProgress)\r
+       {\r
+               dmaInProgress = 0;\r
+               dmaBuffer = NULL;\r
+               dmaSentCount = 0;\r
+               dmaTotalCount = 0;\r
+               CyDmaChSetRequest(scsiDmaTxChan, CY_DMA_CPU_TERM_CHAIN);\r
+               CyDmaChSetRequest(scsiDmaRxChan, CY_DMA_CPU_TERM_CHAIN);\r
+               trace(trace_spinDMAReset);\r
+               while (!(scsiTxDMAComplete && scsiRxDMAComplete)) {}\r
+\r
+               CyDmaChDisable(scsiDmaTxChan);\r
+               CyDmaChDisable(scsiDmaRxChan);\r
+       }\r
+\r
        // Set the Clear bits for both SCSI device FIFOs\r
        scsiTarget_AUX_CTL = scsiTarget_AUX_CTL | 0x03;\r
 \r
@@ -153,13 +422,130 @@ void scsiPhyReset()
        // Allow the FIFOs to fill up again.\r
        SCSI_ClearPin(SCSI_Out_RST);\r
        scsiTarget_AUX_CTL = scsiTarget_AUX_CTL & ~(0x03);\r
+\r
+       SCSI_Parity_Error_Read(); // clear sticky bits\r
 }\r
 \r
+static void scsiPhyInitDMA()\r
+{\r
+       // One-time init only.\r
+       if (scsiDmaTxChan == CY_DMA_INVALID_CHANNEL)\r
+       {\r
+               scsiDmaRxChan =\r
+                       SCSI_RX_DMA_DmaInitialize(\r
+                               1, // Bytes per burst\r
+                               1, // request per burst\r
+                               HI16(CYDEV_PERIPH_BASE),\r
+                               HI16(CYDEV_SRAM_BASE)\r
+                               );\r
+\r
+               scsiDmaTxChan =\r
+                       SCSI_TX_DMA_DmaInitialize(\r
+                               1, // Bytes per burst\r
+                               1, // request per burst\r
+                               HI16(CYDEV_SRAM_BASE),\r
+                               HI16(CYDEV_PERIPH_BASE)\r
+                               );\r
+               \r
+               CyDmaChDisable(scsiDmaRxChan);\r
+               CyDmaChDisable(scsiDmaTxChan);\r
+\r
+               scsiDmaRxTd[0] = CyDmaTdAllocate();\r
+               scsiDmaTxTd[0] = CyDmaTdAllocate();\r
+\r
+               SCSI_RX_DMA_COMPLETE_StartEx(scsiRxCompleteISR);\r
+               SCSI_TX_DMA_COMPLETE_StartEx(scsiTxCompleteISR);\r
+       }\r
+}\r
+\r
+\r
 void scsiPhyInit()\r
 {\r
+       scsiPhyInitDMA();\r
+\r
        SCSI_RST_ISR_StartEx(scsiResetISR);\r
+}\r
+\r
+// 1 = DBx error\r
+// 2 = Parity error\r
+// 4 = MSG error\r
+// 8 = CD error\r
+// 16 = IO error\r
+// 32 = other error\r
+int scsiSelfTest()\r
+{\r
+       int result = 0;\r
+\r
+       // TEST DBx and DBp\r
+       int i;\r
+       SCSI_Out_Ctl_Write(1); // Write bits manually.\r
+       SCSI_CTL_PHASE_Write(__scsiphase_io); // Needed for parity generation\r
+       for (i = 0; i < 256; ++i)\r
+       {\r
+               SCSI_Out_Bits_Write(i);\r
+               scsiDeskewDelay();\r
+               if (scsiReadDBxPins() != (i & 0xff))\r
+               {\r
+                       result |= 1;\r
+               }\r
+               if (Lookup_OddParity[i & 0xff] != SCSI_ReadPin(SCSI_In_DBP))\r
+               {\r
+                       result |= 2;\r
+               }\r
+       }\r
+       SCSI_Out_Ctl_Write(0); // Write bits normally.\r
+\r
+       // TEST MSG, CD, IO\r
+       for (i = 0; i < 8; ++i)\r
+       {\r
+               SCSI_CTL_PHASE_Write(i);\r
+               scsiDeskewDelay();\r
+\r
+               if (SCSI_ReadPin(SCSI_In_MSG) != !!(i & __scsiphase_msg))\r
+               {\r
+                       result |= 4;\r
+               }\r
+               if (SCSI_ReadPin(SCSI_In_CD) != !!(i & __scsiphase_cd))\r
+               {\r
+                       result |= 8;\r
+               }\r
+               if (SCSI_ReadPin(SCSI_In_IO) != !!(i & __scsiphase_io))\r
+               {\r
+                       result |= 16;\r
+               }\r
+       }\r
+       SCSI_CTL_PHASE_Write(0);\r
 \r
-       // Interrupts may have already been directed to the (empty)\r
-       // standard ISR generated by PSoC Creator.\r
-       SCSI_RST_ClearInterrupt();\r
+       uint32_t signalsOut[] = { SCSI_Out_ATN, SCSI_Out_BSY, SCSI_Out_RST, SCSI_Out_SEL };\r
+       uint32_t signalsIn[] = { SCSI_Filt_ATN, SCSI_Filt_BSY, SCSI_Filt_RST, SCSI_Filt_SEL };\r
+\r
+       for (i = 0; i < 4; ++i)\r
+       {\r
+               SCSI_SetPin(signalsOut[i]);\r
+               scsiDeskewDelay();\r
+\r
+               int j;\r
+               for (j = 0; j < 4; ++j)\r
+               {\r
+                       if (i == j)\r
+                       {\r
+                               if (! SCSI_ReadFilt(signalsIn[j]))\r
+                               {\r
+                                       result |= 32;\r
+                               }\r
+                       }\r
+                       else\r
+                       {\r
+                               if (SCSI_ReadFilt(signalsIn[j]))\r
+                               {\r
+                                       result |= 32;\r
+                               }\r
+                       }\r
+               }\r
+               SCSI_ClearPin(signalsOut[i]);\r
+       }\r
+       return result;\r
 }\r
+\r
+\r
+#pragma GCC pop_options\r